mmcodecreg.h revision 4ab75253616c6d68e967c10221bb663c0bfa99df
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License, Version 1.0 only
* (the "License"). You may not use this file except in compliance
* with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2005 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#ifndef _SYS_MMCODECREG_H
#define _SYS_MMCODECREG_H
#pragma ident "%Z%%M% %I% %E% SMI"
/*
* MMCODEC - Multi-Media Codec operates over the CHI bus and interfaces
* with DBRI.
*/
#ifdef __cplusplus
extern "C" {
#endif
/*
* Data Mode timeslot structure
*/
typedef union {
struct {
/* time slot 5 */
unsigned char
/* time slot 6 */
unsigned char
:1,
/* time slot 7 */
unsigned char
/* time slot 8 */
unsigned char
} r;
/*
* Time Slot 5 data mode bit defines
*/
#define MMCODEC_MIN_ATEN (0) /* Minimum attenuation */
/*
* Time Slot 6 data mode bit defines
*/
/*
* Time Slot 7 data mode bit defines
*/
#define MMCODEC_MIN_GAIN (0)
#define MMCODEC_MAX_GAIN (15)
/*
* Time Slot 8 data mode bit defines
*/
#define MMCODEC_MA_MIN_ATEN (0)
#define MMCODEC_MA_MAX_ATEN (15)
/*
* Control Mode timeslot structure
*/
typedef union {
struct {
/* time slot 1 */
unsigned char
:3,
mb:1,
/* time slot 2 */
unsigned char
:1,
/* time slot 3 */
unsigned char
:2,
/* time slot 4 */
unsigned char
:6,
/* time slot 5 */
unsigned char
:6;
/* time slot 6 */
unsigned char
:8; /* reserved */
/* time slot 7 */
unsigned char
/* time slot 8 */
unsigned char
:8; /* reserved */
} r;
/*
* Time Slot 1 control mode bit defines
*/
#define MMCODEC_VS0 0x0
#define MMCODEC_VS1 0x1
/*
* Time Slot 2 data frequency rate bit defines
*/
#define MMCODEC_DFR_8000 0x0
#define MMCODEC_DFR_5513 0x0
#define MMCODEC_DFR_16000 0x1
#define MMCODEC_DFR_11025 0x1
#define MMCODEC_DFR_27429 0x2
#define MMCODEC_DFR_18900 0x2
#define MMCODEC_DFR_32000 0x3
#define MMCODEC_DFR_22050 0x3
#define MMCODEC_DFR_37800 0x4
#define MMCODEC_DFR_44100 0x5
#define MMCODEC_DFR_48000 0x6
#define MMCODEC_DFR_33075 0x6
#define MMCODEC_DFR_9600 0x7
#define MMCODEC_DFR_6615 0x7
/*
* Time Slot 3 master clock bit defines
*/
/*
* Time Slot 4 loopback bit defines
*/
/*
* General MMCODEC defines
*/
/* XXX - This potentially belongs in something like dbri_sun_chi.h or ... */
#define SCHI_SET_DATA_MODE DBRI_PIO_3
#define SCHI_SET_CTRL_MODE (0 << 3)
#define SCHI_SET_INT_PDN DBRI_PIO_2
#define SCHI_CLR_INT_PDN (0 << 2)
#define SCHI_SET_RESET (0 << 1)
#define SCHI_CLR_RESET DBRI_PIO_1
#define SCHI_SET_PDN DBRI_PIO_0
#define SCHI_CLR_PDN (0)
#define SCHI_ENA_MODE DBRI_PIO3_EN
#define SCHI_ENA_INT_PDN DBRI_PIO2_EN
#define SCHI_ENA_RESET DBRI_PIO1_EN
#define SCHI_ENA_PDN DBRI_PIO0_EN
#define SCHI_ENA_ALL (0xF0)
#ifdef __cplusplus
}
#endif
#endif /* _SYS_MMCODECREG_H */