mace.h revision 297a64e7779d7bd7140d1f3f2fa5db171aa21569
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License, Version 1.0 only
* (the "License"). You may not use this file except in compliance
* with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright (c) 1992,1997-1998 by Sun Microsystems, Inc.
* All rights reserved.
*/
#ifndef _SYS_MACE_H
#define _SYS_MACE_H
#pragma ident "%Z%%M% %I% %E% SMI"
#ifdef __cplusplus
extern "C" {
#endif
/*
* Declarations and definitions specific to the Am79C940 MACE
* Media Access Controller for Ethernet
*
* The MACE is a slave register-based Ethernet (IEEE 802.3)
* controller chip combining MAC core, Manchester endec, and SIA
* for AUI (10BASE5), DAI (10BASET), and GPSI network interfaces.
* All registers are 8bits wide externally except Transmit
* and Receive FIFO registers which are 16bits wide externally.
* Some registers are internally wider than 8bits, these
* have bit width denoted [xx-yy], and are accessed by
*/
/*
* MACE Register Set.
*/
struct mace {
};
/*
* MACE Register Bit Masks.
* XXX add right-shift values later.
*/
#define MACE_BIU_XMTSP4 (0) /* 4byte transmit start */
#define MACE_CHIPID1_MAGIC (0x09)
#ifdef __cplusplus
}
#endif
#endif /* _SYS_MACE_H */