bmac.h revision 297a64e7779d7bd7140d1f3f2fa5db171aa21569
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License, Version 1.0 only
* (the "License"). You may not use this file except in compliance
* with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright (c) 1992,1997-1998 by Sun Microsystems, Inc.
* All rights reserved.
*/
#ifndef _SYS_BMAC_H
#define _SYS_BMAC_H
#pragma ident "%Z%%M% %I% %E% SMI"
#ifdef __cplusplus
extern "C" {
#endif
/*
* Declarations and definitions specific to the BigMAC chip.
*
* protocol based interface. The QEC will control the transfer of data
* between the host memory, buffer memory and the BigMAC. When transmitting
* a frame will be moved from the Sbus to buffer memory. When an entire
* frame is present in the buffer memory, the QEC will move the data from
* the buffer memory to BigMAC. Same is the case while receiving. When the
* entire frame is present in the buffer memory, QEC will move frame from
* buffer memory to host's memory.
*
*/
/*
* BigMAC Register Set.
* BigMAC addresses map on a SBus word boundry. So all registers are
* declared for a size of 32 bits. Registers that use fewer than 32
* bits will return 0 in the bits not used.
* XXX Do spaces between registers need to be paded.
*/
struct bmac {
};
/*
* BigMAC Register Bit Masks.
* XXX add right-shift values later.
*/
struct bmactcvr {
};
/* P1 Board */
/* P1.5 Board */
#define BMAC_TPAL2_MDC_BIT_POS 0 /* Mgmt. data clock */
/*
* Management Frame Structure:
* <IDLE> <ST><OP><PHYAD><REGAD><TA> <DATA> <IDLE>
* READ: <01><10><AAAAA><RRRRR><Z0><DDDDDDDDDDDDDDDD>
* WRITE: <01><01><AAAAA><RRRRR><10><DDDDDDDDDDDDDDDD>
*/
#define BMAC_EXTERNAL_PHYAD 0x0
#define BMAC_INTERNAL_PHYAD 0x1
#define BMAC_MII_CTLREG 0x0
#define BMAC_MII_STATREG 0x1
/* Control Register Bit Definitions */
/* Status Register Bit Definitions */
#define BMAC_MII_STAT_EXT_CAP (1 << 0)
#ifdef __cplusplus
}
#endif
#endif /* _SYS_BMAC_H */