pcie_error.c revision f41150baf74bdaf964ddfe42d865d3c2380b3623
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin * CDDL HEADER START
7c2fbfb345896881c631598ee3852ce9ce33fb07April Chin * The contents of this file are subject to the terms of the
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin * Common Development and Distribution License (the "License").
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin * You may not use this file except in compliance with the License.
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin * See the License for the specific language governing permissions
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da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin * When distributing Covered Code, include this CDDL HEADER in each
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
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da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin * CDDL HEADER END
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin * Copyright 2008 Sun Microsystems, Inc. All rights reserved.
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin * Use is subject to license terms.
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#pragma ident "%Z%%M% %I% %E% SMI"
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin * Library file that has code for PCIe error handling
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#else /* DEBUG */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#endif /* DEBUG */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin/* Variables to control error settings */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin/* Device Command Register */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin/* PCI-Express Device Control Register */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin/* PCI-Express AER Root Control Register */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#if defined(__xpv)
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#endif /* __xpv */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin/* PCI-Express Root Error Command Register */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin * PCI-Express related masks (AER only)
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin * Can be defined to mask off certain types of AER errors
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin * By default all are set to 0; as no errors are masked
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin * PCI-Express related severity (AER only)
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin * Used to set the severity levels of errors detected by devices on the PCI
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin * Express fabric, which in turn results in either a fatal or nonfatal error
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin * message to the root complex. A set bit (1) indictates a fatal error, an
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin * unset one is nonfatal. For more information refer to the PCI Express Base
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin * Specification and the PCI Express to PCI/PCI-X Bridge Specification.
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin * default values are set below:
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chinuint32_t pcie_aer_uce_severity = PCIE_AER_UCE_MTLP | PCIE_AER_UCE_RO | \
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin PCIE_AER_UCE_FCP | PCIE_AER_UCE_SD | PCIE_AER_UCE_DLP | \
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chinuint32_t pcie_aer_suce_severity = PCIE_AER_SUCE_SERR_ASSERT | \
boolean_t *);
_init(void)
_fini()
return (DDI_SUCCESS);
if (pcie_serr_disable_flag &&
return (DDI_SUCCESS);
return (DDI_SUCCESS);
return (DDI_SUCCESS);
return (DDI_SUCCESS);
return (DDI_SUCCESS);
if (val == 0)
if (val == 0)
#if defined(__xpv)
if (!pcie_aer_disable_flag) {
if (!pcie_serr_disable_flag) {
if (cap_ptr) {
static uint16_t
return (PCI_CAP_NEXT_PTR_NULL);
return (PCI_CAP_NEXT_PTR_NULL);
return (caps_ptr);
static uint16_t
return (PCIE_EXT_CAP_NEXT_PTR_NULL);
#ifdef DEBUG
if (!pcie_error_debug_flags)