context.c revision ae115bc77f6fcde83175c75b4206dc2e50747966
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License, Version 1.0 only
* (the "License"). You may not use this file except in compliance
* with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2004 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#pragma ident "%Z%%M% %I% %E% SMI"
#include <sys/controlregs.h>
#include <sys/sysmacros.h>
#include <amd64/machregs.h>
#include <amd64/segments.h>
#include <amd64/bootops64.h>
#include <amd64/bootsvcs64.h>
#include <amd64/amd64_page.h>
/*
* This save area is initialized by amd64_exitto(), and used to
* restore the state of the machine before invoking various
* bootops.
*
* However, it needs to be mapped 1:1 so that we can reference it
* while paging is disabled. This is achieved via mapfile trickery;
* we glom the entire program into one contiguous segment.
*/
struct i386_machregs exitto_i386_machregs;
/*CSTYLED*/
/*CSTYLED*/
/*CSTYLED*/
static void
{
/*
* TSS
*/
/*
* All exceptions but #DF will run on the exception stack.
*/
&amd64_exception_stack[sizeof (amd64_exception_stack)];
/*
* #DF (double fault) gets its own private stack.
*/
&amd64_dblfault_stack[sizeof (amd64_dblfault_stack)];
/*
* GDT
*/
/*
* 32-bit legacy or compatibility mode for data.
* Maps entire 4G address space.
*/
/*
* 32-bit legacy or compatibility mode for code.
* Maps entire 4G address space.
*/
/*
* 64-bit long mode for data. XXX don't really need this.
* Maps entire 64-bit address space by definition.
*/
/*
* 64-bit long mode for code.
* Maps entire 64-bit address space by definition.
*/
/*
* 64-bit long mode TSS.
*/
}
static void
{
int i;
/*
* IDT
*
* First initialize all entries to reserve trap then overwrite
* the important ones with specific handlers.
*
* XXX how big does this idt really need to be ? I suspect
* only large enough to hold kmdb's soft int?
*
* XX64 fbsd only uses interrupt gates for all. Perhaps
* This is good for amd64 since we want to block maskable
* interrupts once we take an exception?
*/
for (i = 0; i < NIDT; i++)
/*
* double fault handler gets its own private stack (tss.ist2).
*/
/*
* T_EXTOVRFLT coprocessor-segment-overrun not supported.
*/
/*
* 15 reserved.
*/
/*
* 20-31 reserved
*/
for (i = 20; i < 32; i++)
/*
* XX64 -- why not resvtrap in initial programming??
* either way, move this to the top so that the defaults
* are set together.
*/
}
/*
* Note that when rsp is being pushed, like the processor, we must
* ensure that the value of the stack pointer at the beginning of the
* instruction is the one that is pushed, NOT the value after.
*/
struct amd64_machregs *
{
extern struct boot_syscalls *sysp;
extern Elf64_Boot *elfbootvecELF64;
struct boot_syscalls64 *sysp64;
/*
* terminate stack walks with a null RBP value.
*/
/*
* push in amd64_machregs order.
*/
/*
* XX64: Note that boot enables CR4_PGE (global pages)
* and Joe has discovered errata that warns against
* mixing this. Need to investigate.
*/
/*
* XX64 - CR0_PG already set?
*/
return ((struct amd64_machregs *)rsp);
}