kaif_resume.s revision ae115bc77f6fcde83175c75b4206dc2e50747966
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License, Version 1.0 only
* (the "License"). You may not use this file except in compliance
* with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2004 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#pragma ident "%Z%%M% %I% %E% SMI"
#include <sys/asm_linkage.h>
#include <sys/segments.h>
#include <sys/x86_archext.h>
#include <sys/controlregs.h>
#include <kmdb/kaif_asmutil.h>
#include <kmdb/kaif_off.h>
#include <kmdb/kmdb_dpi_isadep.h>
#include <mdb/mdb_kreg.h>
/*
* Given the address of the current CPU's cpusave area in %rax, the following
* macro restores the debugging state to said CPU. Restored state includes
* the debug registers from the global %dr variables, and debugging MSRs from
* the CPU save area. This code would be in a separate routine, but for the
* fact that some of the MSRs are jump-sensitive. As such, we need to minimize
* the number of jumps taken subsequent to the update of said MSRs. We can
* remove one jump (the ret) by using a macro instead of a function for the
* debugging state restoration code.
*
* Takes the cpusave area in %rdi as a parameter, clobbers %rax-%rdx
*/
#define KAIF_RESTORE_DEBUGGING_STATE \
\
/* \
* Write any requested MSRs. \
*/ \
je 3f; \
1: \
je 3f; \
\
jne 2f; \
\
wrmsr; \
2: \
jmp 1b; \
3: \
/* \
* We must not branch after re-enabling LBR. If \
* kaif_wsr_wrexit_msr is set, it contains the number \
* of the MSR that controls LBR. kaif_wsr_wrexit_valp \
* contains the value that is to be written to enable \
* LBR. \
*/ \
je 1f; \
\
\
wrmsr; \
1:
#if defined(__lint)
/*ARGSUSED*/
void
{
}
#else /* __lint */
#endif /* !__lint */
/*
* Resume the world. The code that calls kaif_resume has already
* decided whether or not to restore the IDT.
*/
#if defined(__lint)
void
kaif_resume(void)
{
}
#else /* __lint */
/* cpusave in %rdi, debugger command in %rsi */
/*
* Send this CPU back into the world
*/
#endif /* __lint */
#if !defined(__lint)
/* cpusave is still in %rdi */
/*
* When we replaced the kernel's handlers in the IDT, we made note of
* the handlers being replaced, thus allowing us to pass traps directly
* to said handlers here. We won't have any registers available for use
* after we start popping, and we know we're single-threaded here, so
* we have to use a global to store the handler address.
*/
/*
* The trap handler will expect the stack to be in trap order, with
* %rip being the last entry. Our stack is currently in mdb_kreg.h
* order, so we'll need to pop (and restore) our way back down.
*/
/*NOTREACHED*/
/*
* Reboot the system. This routine is to be called only by the master
* CPU.
*/
je 1f
/* psm_shutdown is set in the kernel, so we'll try it */
1: /*
* psm_shutdown didn't work or, it wasn't set. Let's try the time-
* honored method for getting things done on Intel machines --
* sacrifice random bits to random BIOS gods.
*/
/*NOTREACHED*/
#endif /* !__lint */