Searched refs:regs (Results 1 - 25 of 108) sorted by relevance

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/vbox/src/VBox/Devices/Graphics/BIOS/tests/
H A Dtestbios.c39 void int10ax0003(struct REGPACK *regs) argument
41 regs->r_ax=0x0003;
42 intr(0x10,regs);
45 void int10ax02(struct REGPACK *regs) argument
47 regs->r_ax=0x0200;
48 regs->r_bx=0x0000;
49 regs->r_dx=0x1710;
50 intr(0x10,regs);
54 void int10ax03(struct REGPACK *regs) argument
56 regs
62 int10ax0501(struct REGPACK *regs) argument
72 int10ax0602(struct REGPACK *regs) argument
82 int10ax0702(struct REGPACK *regs) argument
92 int10ax08(struct REGPACK *regs) argument
99 int10ax09(struct REGPACK *regs) argument
114 int10ax0a(struct REGPACK *regs) argument
124 int10ax0f(struct REGPACK *regs) argument
132 int10ax1b(struct REGPACK *regs) argument
156 int10ax13(struct REGPACK *regs) argument
174 switch_50(struct REGPACK *regs) argument
186 exec_function(struct REGPACK *regs) argument
314 show_regs(struct REGPACK *regs) argument
329 struct REGPACK regs; local
339 struct REGPACK regs; local
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/vbox/src/VBox/Devices/PC/ipxe/src/arch/i386/core/
H A Ddumpregs.c18 ix86->regs.eax, ix86->regs.ebx, ix86->regs.ecx,
19 ix86->regs.edx, ix86->regs.esi, ix86->regs.edi,
20 ix86->regs.ebp, ix86->regs.esp,
H A Drelocate.c62 if ( ix86->regs.ebp && ( ix86->regs.ebp < max ) ) {
63 max = ix86->regs.ebp;
133 ix86->regs.esi = start;
134 ix86->regs.edi = new_start;
135 ix86->regs.ecx = size;
/vbox/src/VBox/ExtPacks/VBoxDTrace/onnv/lib/libdtrace/i386/
H A DMakefile31 DLIBSRCS = regs.d
40 CLEANFILES += regs.sed regs.d
46 ../$(MACH)/regs.d: regs.sed regs.d.in
47 sed -f regs.sed < regs.d.in > $@
/vbox/src/VBox/Devices/PC/ipxe/src/drivers/net/
H A Dskeleton.h18 void *regs; member in struct:skeleton_nic
H A Dvia-velocity.c235 static void safe_disable_mii_autopoll(struct mac_regs *regs);
237 static void enable_mii_autopoll(struct mac_regs *regs);
240 static u32 mii_check_media_mode(struct mac_regs *regs);
241 static u32 check_connection_type(struct mac_regs *regs);
392 struct mac_regs *regs = vptr->mac_regs; local
395 WORD_REG_BITS_SET(MCFG_PQEN, MCFG_RTGOPT, &regs->MCFG);
396 WORD_REG_BITS_ON(MCFG_VIDFR, &regs->MCFG);
401 mac_set_cam_mask(regs, vptr->vCAMmask, VELOCITY_VLAN_ID_CAM);
402 mac_set_cam_mask(regs, vptr->mCAMmask, VELOCITY_MULTICAST_CAM);
409 WORD_REG_BITS_ON(MCFG_RTGOPT, &regs
427 struct mac_regs *regs = vptr->mac_regs; local
624 struct mac_regs *regs = vptr->mac_regs; local
684 struct mac_regs *regs; local
959 struct mac_regs *regs = vptr->mac_regs; local
989 struct mac_regs *regs = vptr->mac_regs; local
1122 struct mac_regs *regs = vptr->mac_regs; local
1392 safe_disable_mii_autopoll(struct mac_regs *regs) argument
1413 enable_mii_autopoll(struct mac_regs *regs) argument
1446 velocity_mii_read(struct mac_regs *regs, u8 index, u16 * data) argument
1482 velocity_mii_write(struct mac_regs *regs, u8 mii_addr, u16 data) argument
1618 struct mac_regs *regs = vptr->mac_regs; local
1721 mii_check_media_mode(struct mac_regs *regs) argument
1761 check_connection_type(struct mac_regs *regs) argument
1808 struct mac_regs *regs = vptr->mac_regs; local
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H A Dvia-velocity.h1209 #define mac_hw_mibs_init(regs) {\
1210 BYTE_REG_BITS_ON(MIBCR_MIBFRZ,&((regs)->MIBCR));\
1211 BYTE_REG_BITS_ON(MIBCR_MIBCLR,&((regs)->MIBCR));\
1213 while (BYTE_REG_BITS_IS_ON(MIBCR_MIBCLR,&((regs)->MIBCR)));\
1214 BYTE_REG_BITS_OFF(MIBCR_MIBFRZ,&((regs)->MIBCR));\
1217 #define mac_read_isr(regs) readl(&((regs)->ISR))
1218 #define mac_write_isr(regs, x) writel((x),&((regs)->ISR))
1219 #define mac_clear_isr(regs) write
1283 mac_get_cam_mask(struct mac_regs *regs, u8 * mask, enum velocity_cam_type cam_type) argument
1318 mac_set_cam_mask(struct mac_regs *regs, u8 * mask, enum velocity_cam_type cam_type) argument
1352 mac_set_cam(struct mac_regs *regs, int idx, u8 * addr, enum velocity_cam_type cam_type) argument
1398 mac_get_cam(struct mac_regs *regs, int idx, u8 * addr, enum velocity_cam_type cam_type) argument
1441 mac_wol_reset(struct mac_regs *regs) argument
1915 struct mac_regs *regs = vptr->mac_regs; local
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H A Dmyson.c69 bcr = readl ( myson->regs + MYSON_BCR );
70 writel ( ( bcr | MYSON_BCR_SWR ), myson->regs + MYSON_BCR );
76 if ( readl ( myson->regs + MYSON_BCR ) & MYSON_BCR_SWR ) {
82 bcr = readl ( myson->regs + MYSON_BCR );
86 writel ( bcr, myson->regs + MYSON_BCR );
107 writel ( MYSON_ROM_AUTOLD, myson->regs + MYSON_ROM_MII );
113 if ( readl ( myson->regs + MYSON_ROM_MII ) & MYSON_ROM_AUTOLD ){
136 writel ( 0, myson->regs + MYSON_IMR );
197 writel ( address, myson->regs + ring->reg );
222 writel ( 0, myson->regs
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/vbox/src/VBox/Devices/PC/BIOS/
H A Dtimepci.c101 void BIOSCALL int70_function(pusha_regs_t regs, uint16_t ds, uint16_t es, iret_addr_t iret_addr) argument
148 void BIOSCALL int1a_function(pusha_regs_t regs, uint16_t ds, uint16_t es, iret_addr_t iret_addr) argument
153 regs.u.r16.ax, regs.u.r16.bx, regs.u.r16.cx, regs.u.r16.dx, ds);
156 switch (regs.u.r8.ah) {
159 regs.u.r16.cx = BiosData->ticks_high;
160 regs.u.r16.dx = BiosData->ticks_low;
161 regs
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H A Dserial.c46 void BIOSCALL int14_function(pusha_regs_t regs, uint16_t es, uint16_t ds, volatile iret_addr_t iret_addr) argument
53 addr = read_word(0x0040, (regs.u.r16.dx << 1));
54 timeout = read_byte(0x0040, 0x007C + regs.u.r16.dx);
55 if ((regs.u.r16.dx < 4) && (addr > 0)) {
56 switch (regs.u.r8.ah) {
59 if (regs.u.r8.al & 0xE0 == 0) {
63 val16 = 0x600 >> ((regs.u.r8.al & 0xE0) >> 5);
67 outb(addr+3, regs.u.r8.al & 0x1F);
68 regs.u.r8.ah = inb(addr+5);
69 regs
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H A Dparallel.c46 void BIOSCALL int17_function(pusha_regs_t regs, uint16_t es, uint16_t ds, volatile iret_addr_t iret_addr) argument
53 addr = read_word(0x0040, (regs.u.r16.dx << 1) + 8);
54 if ((regs.u.r8.ah < 3) && (regs.u.r16.dx < 3) && (addr > 0)) {
55 timeout = read_byte(0x0040, 0x0078 + regs.u.r16.dx) << 8;
56 if (regs.u.r8.ah == 0) {
57 outb(addr, regs.u.r8.al);
65 if (regs.u.r8.ah == 1) {
71 regs.u.r8.ah = (val8 ^ 0x48);
72 if (!timeout) regs
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H A Dps2mouse.c146 void BIOSCALL int15_function_mouse(pusha_regs_t regs, uint16_t ES, uint16_t DS, volatile uint16_t FLAGS) argument
155 BX_DEBUG_INT15_MS("int15 AX=%04x\n",regs.u.r16.ax);
168 if (regs.u.r8.al > 7) {
172 regs.u.r8.ah = 1;
179 regs.u.r8.ah = 0;
181 switch (regs.u.r8.al) {
184 if (regs.u.r8.bh > 1) {
185 BX_DEBUG_INT15_MS("INT 15h C2 AL=0, BH=%02x\n", (unsigned) regs.u.r8.bh);
188 regs.u.r8.ah = 1;
195 regs
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/vbox/src/VBox/Devices/PC/ipxe/src/arch/i386/include/
H A Dgdbmach.h49 static inline void gdbmach_set_pc ( gdbreg_t *regs, gdbreg_t pc ) { argument
50 regs [ GDBMACH_EIP ] = pc;
53 static inline void gdbmach_set_single_step ( gdbreg_t *regs, int step ) { argument
54 regs [ GDBMACH_EFLAGS ] &= ~( 1 << 8 ); /* Trace Flag (TF) */
55 regs [ GDBMACH_EFLAGS ] |= ( step << 8 );
/vbox/src/VBox/Devices/PC/ipxe/src/arch/x86_64/include/
H A Dgdbmach.h36 static inline void gdbmach_set_pc ( gdbreg_t *regs, gdbreg_t pc ) { argument
37 regs [ GDBMACH_EIP ] = pc;
40 static inline void gdbmach_set_single_step ( gdbreg_t *regs, int step ) { argument
41 regs [ GDBMACH_EFLAGS ] &= ~( 1 << 8 ); /* Trace Flag (TF) */
42 regs [ GDBMACH_EFLAGS ] |= ( step << 8 );
/vbox/src/VBox/Devices/PC/ipxe/src/arch/i386/interface/syslinux/
H A Dcomboot_call.c234 switch ( ix86->regs.ah ) {
243 ix86->regs.al = getchar( );
246 if ( ix86->regs.al == 0x0A )
247 ix86->regs.al = 0x0D;
249 if ( ix86->regs.ah == 0x01 )
250 putchar ( ix86->regs.al );
256 putchar ( ix86->regs.dl );
261 serial_putc ( ix86->regs.dl );
266 print_user_string ( ix86->segs.ds, ix86->regs.dx, '$' );
272 ix86->regs
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/vbox/src/VBox/Additions/x11/x11include/mesa-7.2/src/mesa/drivers/dri/common/
H A Dmmx.h163 #define mmx_r2r(op, regs, regd) \
166 __asm__ __volatile__ ("movq %%" #regs ", %0" \
169 fprintf(stderr, #op "_r2r(" #regs "=0x%016llx, ", mmx_trace.q); \
174 __asm__ __volatile__ (#op " %" #regs ", %" #regd); \
217 #define mmx_r2r(op, regs, regd) \
218 __asm__ __volatile__ (#op " %" #regs ", %" #regd)
236 #define movq_r2r(regs, regd) mmx_r2r(movq, regs, regd)
251 #define movd_r2r(regs, regd) mmx_r2r(movd, regs, reg
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/vbox/src/libs/xpcom18a4/xpcom/reflect/xptcall/src/md/unix/
H A Dxptcinvoke_irix.cpp54 nsXPTCVariant* s, PRUint64 *regs)
56 #define N_ARG_REGS 7 /* 8 regs minus 1 for "this" ptr */
62 regs[i] = (PRUint64)s->ptr;
73 ((PRInt64*)regs)[i] = s->val.i8;
79 ((PRInt64*)regs)[i] = s->val.i16;
85 ((PRInt64*)regs)[i] = s->val.i32;
91 ((PRInt64*)regs)[i] = s->val.i64;
100 regs[i] = s->val.u8;
106 regs[i] = s->val.u16;
112 regs[
53 invoke_copy_to_stack(PRUint64* d, PRUint32 paramCount, nsXPTCVariant* s, PRUint64 *regs) argument
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/vbox/src/libs/xpcom18a4/xpcom/reflect/xptcall/src/md/win32/
H A Dxptcinvoke_alpha.cpp52 nsXPTCVariant* s, PRUint64 *regs)
54 #define N_ARG_REGS 5 /* 6 regs minus 1 for "this" ptr */
60 regs[i] = (PRUint32)s->ptr;
71 ((PRInt64*)regs)[i] = s->val.i8;
77 ((PRInt64*)regs)[i] = s->val.i16;
83 ((PRInt64*)regs)[i] = s->val.i32;
89 ((PRInt64*)regs)[i] = s->val.i64;
98 regs[i] = s->val.u8;
104 regs[i] = s->val.u16;
110 regs[
51 invoke_copy_to_stack(PRUint64* d, PRUint32 paramCount, nsXPTCVariant* s, PRUint64 *regs) argument
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/vbox/src/VBox/Devices/EFI/Firmware/StdLib/Include/Ipf/machine/
H A Ddb_machdep.h53 #define PC_REGS(regs) ((db_addr_t)(regs)->tf_special.__spare == 0) ? \
54 ((db_addr_t)(regs)->tf_special.rp) : \
55 ((db_addr_t)(regs)->tf_special.iip + (((regs)->tf_special.psr>>41) & 3))
59 #define PC_REGS(regs) ((db_addr_t)(regs)->tf_special.iip + (((regs)->tf_special.psr>>41) & 3))
62 #define db_set_single_step(regs) ((regs)
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/vbox/src/VBox/Additions/x11/x11include/xorg-server-1.3.0.0/
H A Dxf86Pci.h400 /* User defined cfg space regs */
644 pciCfgRegs regs; member in union:pci_cfg_spc
676 #define pci_device_vendor cfgspc.regs.dv_id.device_vendor
677 #define pci_vendor cfgspc.regs.dv_id.dv.vendor
678 #define pci_device cfgspc.regs.dv_id.dv.device
679 #define pci_status_command cfgspc.regs.stat_cmd.status_command
680 #define pci_command cfgspc.regs.stat_cmd.sc.command
681 #define pci_status cfgspc.regs.stat_cmd.sc.status
682 #define pci_class_revision cfgspc.regs.class_rev.class_revision
683 #define pci_rev_id cfgspc.regs
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/vbox/src/VBox/Additions/x11/x11include/xorg-server-1.4.2/
H A Dxf86Pci.h400 /* User defined cfg space regs */
644 pciCfgRegs regs; member in union:pci_cfg_spc
676 #define pci_device_vendor cfgspc.regs.dv_id.device_vendor
677 #define pci_vendor cfgspc.regs.dv_id.dv.vendor
678 #define pci_device cfgspc.regs.dv_id.dv.device
679 #define pci_status_command cfgspc.regs.stat_cmd.status_command
680 #define pci_command cfgspc.regs.stat_cmd.sc.command
681 #define pci_status cfgspc.regs.stat_cmd.sc.status
682 #define pci_class_revision cfgspc.regs.class_rev.class_revision
683 #define pci_rev_id cfgspc.regs
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/vbox/src/VBox/Additions/x11/x11include/4.3/programs/Xserver/hw/xfree86/os-support/bus/
H A Dxf86Pci.h372 /* User defined cfg space regs */
616 pciCfgRegs regs; member in union:pci_cfg_spc
655 #define pci_device_vendor cfgspc.regs.dv_id.device_vendor
656 #define pci_vendor cfgspc.regs.dv_id.dv.vendor
657 #define pci_device cfgspc.regs.dv_id.dv.device
658 #define pci_status_command cfgspc.regs.stat_cmd.status_command
659 #define pci_command cfgspc.regs.stat_cmd.sc.command
660 #define pci_status cfgspc.regs.stat_cmd.sc.status
661 #define pci_class_revision cfgspc.regs.class_rev.class_revision
662 #define pci_rev_id cfgspc.regs
[all...]
/vbox/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/
H A Dxf86Pci.h401 /* User defined cfg space regs */
645 pciCfgRegs regs; member in union:pci_cfg_spc
677 #define pci_device_vendor cfgspc.regs.dv_id.device_vendor
678 #define pci_vendor cfgspc.regs.dv_id.dv.vendor
679 #define pci_device cfgspc.regs.dv_id.dv.device
680 #define pci_status_command cfgspc.regs.stat_cmd.status_command
681 #define pci_command cfgspc.regs.stat_cmd.sc.command
682 #define pci_status cfgspc.regs.stat_cmd.sc.status
683 #define pci_class_revision cfgspc.regs.class_rev.class_revision
684 #define pci_rev_id cfgspc.regs
[all...]
/vbox/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/
H A Dxf86Pci.h401 /* User defined cfg space regs */
645 pciCfgRegs regs; member in union:pci_cfg_spc
678 #define pci_device_vendor cfgspc.regs.dv_id.device_vendor
679 #define pci_vendor cfgspc.regs.dv_id.dv.vendor
680 #define pci_device cfgspc.regs.dv_id.dv.device
681 #define pci_status_command cfgspc.regs.stat_cmd.status_command
682 #define pci_command cfgspc.regs.stat_cmd.sc.command
683 #define pci_status cfgspc.regs.stat_cmd.sc.status
684 #define pci_class_revision cfgspc.regs.class_rev.class_revision
685 #define pci_rev_id cfgspc.regs
[all...]
/vbox/src/recompiler/tests/
H A Dqruncom.c107 env->regs[R_ESP] = (env->regs[R_ESP] & ~0xffff) | ((env->regs[R_ESP] - 2) & 0xffff);
108 *(uint16_t *)seg_to_linear(env->segs[R_SS].selector, env->regs[R_ESP]) = val;
181 env->regs[R_ESP] = 0xfffe;
229 env->regs[R_ESI] = 0x100;
230 env->regs[R_ECX] = 0xff;
231 env->regs[R_EBP] = 0x0900;
232 env->regs[R_EDI] = 0xfffe;
247 ah = (env->regs[R_EA
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