Searched refs:XhcWriteOpReg (Results 1 - 4 of 4) sorted by relevance
| /vbox/src/VBox/Devices/EFI/Firmware/MdeModulePkg/Bus/Pci/XhciDxe/ |
| H A D | Xhci.c | 493 XhcWriteOpReg (Xhc, Offset, State);
496 XhcWriteOpReg (Xhc, Offset, State);
528 XhcWriteOpReg (Xhc, Offset, State);
618 XhcWriteOpReg (Xhc, Offset, State);
623 XhcWriteOpReg (Xhc, Offset, State);
625 XhcWriteOpReg (Xhc, Offset, State);
647 XhcWriteOpReg (Xhc, Offset, State);
655 XhcWriteOpReg (Xhc, Offset, State);
663 XhcWriteOpReg (Xhc, Offset, State);
671 XhcWriteOpReg (Xh
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| H A D | XhciReg.c | 137 XhcWriteOpReg ( function
157 DEBUG ((EFI_D_ERROR, "XhcWriteOpReg: Pci Io Write error: %r at %d\n", Status, Offset));
260 DEBUG ((EFI_D_ERROR, "XhcWriteOpReg: Pci Io Write error: %r at %d\n", Status, Offset));
468 XhcWriteOpReg (Xhc, Offset, Data);
491 XhcWriteOpReg (Xhc, Offset, Data);
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| H A D | XhciReg.h | 256 XhcWriteOpReg (
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| H A D | XhciSched.c | 428 XhcWriteOpReg (Xhc, XHC_CONFIG_OFFSET, Xhc->MaxSlotsEn);
478 XhcWriteOpReg (Xhc, XHC_DCBAAP_OFFSET, XHC_LOW_32BIT(Xhc->DCBAA));
479 XhcWriteOpReg (Xhc, XHC_DCBAAP_OFFSET + 4, XHC_HIGH_32BIT (Xhc->DCBAA));
501 XhcWriteOpReg (Xhc, XHC_CRCR_OFFSET, XHC_LOW_32BIT(CmdRing));
502 XhcWriteOpReg (Xhc, XHC_CRCR_OFFSET + 4, XHC_HIGH_32BIT (CmdRing));
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Completed in 117 milliseconds