/vbox/src/recompiler/ |
H A D | targphys.h | 12 #define TARGET_PHYS_ADDR_MAX UINT32_MAX
|
/vbox/src/VBox/Runtime/testcase/ |
H A D | tstRand.cpp | 76 uint32_t iMin = UINT32_MAX; 112 { 0, UINT32_MAX }, 113 { 0, UINT32_MAX / 2 + UINT32_MAX / 4 }, 114 { 0, UINT32_MAX / 2 + UINT32_MAX / 8 }, 115 { 0, UINT32_MAX / 2 + UINT32_MAX / 16 }, 116 { 0, UINT32_MAX / 2 + UINT32_MAX / 6 [all...] |
H A D | tstRTPoll.cpp | 57 RTTESTI_CHECK(RTPollSetGetCount(hSetInvl) == UINT32_MAX); 70 RTTESTI_CHECK_RC(RTPollSetRemove(hSet, UINT32_MAX), VERR_INVALID_PARAMETER); 76 RTTESTI_CHECK_RC(RTPollSetAdd(hSet, &Handle, RTPOLL_EVT_ERROR, UINT32_MAX), VERR_INVALID_PARAMETER); 77 RTTESTI_CHECK_RC(RTPollSetAdd(hSet, &Handle, UINT32_MAX, 3), VERR_INVALID_PARAMETER); 80 RTTESTI_CHECK_RC(RTPollSetAdd(hSet, NULL, RTPOLL_EVT_ERROR, UINT32_MAX), VERR_INVALID_PARAMETER); 194 uint32_t fEvents = UINT32_MAX; 195 uint32_t id = UINT32_MAX; 200 fEvents = UINT32_MAX; 201 id = UINT32_MAX; 208 fEvents = UINT32_MAX; [all...] |
H A D | tstRTGetOpt.cpp | 199 CHECK(GetState.uIndex == UINT32_MAX); 202 CHECK(GetState.uIndex == UINT32_MAX); 205 CHECK(GetState.uIndex == UINT32_MAX); 208 CHECK(GetState.uIndex == UINT32_MAX); 211 CHECK(GetState.uIndex == UINT32_MAX); 214 CHECK(GetState.uIndex == UINT32_MAX); 217 CHECK(GetState.uIndex == UINT32_MAX); 220 CHECK(GetState.uIndex == UINT32_MAX); 223 CHECK(GetState.uIndex == UINT32_MAX); 226 CHECK(GetState.uIndex == UINT32_MAX); [all...] |
/vbox/src/VBox/Runtime/os2/ |
H A D | rtSemWaitOs2ConvertTimeout.cpp | 41 #define MY_SEM_INDEFINITE_WAIT UINT32_MAX 62 if (uTimeout < UINT32_MAX) 90 if (uTimeout >= UINT32_MAX)
|
/vbox/src/VBox/Additions/x11/x11include/pixman-0.16.0/ |
H A D | pixman-compiler.h | 41 #ifndef UINT32_MAX 42 # define UINT32_MAX (4294967295U) macro
|
/vbox/src/VBox/VMM/VMMR3/cpus/ |
H A D | Intel_Pentium_M_processor_2_00GHz.h | 49 MFX(0x00000010, "IA32_TIME_STAMP_COUNTER", Ia32TimestampCounter, Ia32TimestampCounter, 0, ~(uint64_t)UINT32_MAX, 0), /* value=0x22`4d44782e */ 57 MVX(0x00000034, "P6_UNK_0000_0034", 0x77ff, ~(uint64_t)UINT32_MAX, UINT32_C(0xfff80000)), 67 MVX(0x0000004f, "P6_UNK_0000_004f", 0, ~(uint64_t)UINT32_MAX, 0), /* value=0x0 */ 88 MFX(0x000000c1, "IA32_PMC0", Ia32PmcN, Ia32PmcN, 0, ~(uint64_t)UINT32_MAX, 0), /* value=0x0 */ 89 MFX(0x000000c2, "IA32_PMC1", Ia32PmcN, Ia32PmcN, 0, ~(uint64_t)UINT32_MAX, 0), /* value=0x0 */ 103 MVX(0x00000151, "P6_UNK_0000_0151", 0x3c531fc6, ~(uint64_t)UINT32_MAX, 0), 105 MVX(0x0000015b, "P6_UNK_0000_015b", 0, ~(uint64_t)UINT32_MAX, 0), 106 MFX(0x00000174, "IA32_SYSENTER_CS", Ia32SysEnterCs, Ia32SysEnterCs, 0, ~(uint64_t)UINT32_MAX, 0), /* value=0x8 */ 107 MFX(0x00000175, "IA32_SYSENTER_ESP", Ia32SysEnterEsp, Ia32SysEnterEsp, 0, ~(uint64_t)UINT32_MAX, 0), /* value=0xf78af000 */ 108 MFX(0x00000176, "IA32_SYSENTER_EIP", Ia32SysEnterEip, Ia32SysEnterEip, 0, ~(uint64_t)UINT32_MAX, [all...] |
H A D | AMD_Athlon_64_3200.h | 74 MFX(0x00000174, "IA32_SYSENTER_CS", Ia32SysEnterCs, Ia32SysEnterCs, 0, ~(uint64_t)UINT32_MAX, 0), /* value=0x8 */ 75 MFX(0x00000175, "IA32_SYSENTER_ESP", Ia32SysEnterEsp, Ia32SysEnterEsp, 0, ~(uint64_t)UINT32_MAX, 0), /* value=0x8059e000 */ 76 MFX(0x00000176, "IA32_SYSENTER_EIP", Ia32SysEnterEip, Ia32SysEnterEip, 0, ~(uint64_t)UINT32_MAX, 0), /* value=0x81872950 */ 119 MFX(0xc0000084, "AMD64_SYSCALL_FLAG_MASK", Amd64SyscallFlagMask, Amd64SyscallFlagMask, 0, ~(uint64_t)UINT32_MAX, 0), /* value=0x0 */ 147 MFX(0xc0010111, "AMD_K8_SMM_BASE", AmdK8SmmBase, AmdK8SmmBase, 0, ~(uint64_t)UINT32_MAX, 0), /* value=0x98000 */ 157 MVX(0xc001011b, "AMD_K8_UNK_c001_011b", 0, 0, ~(uint64_t)UINT32_MAX), 159 MFX(0xc0011000, "AMD_K7_MCODE_CTL", AmdK7MicrocodeCtl, AmdK7MicrocodeCtl, 0, ~(uint64_t)UINT32_MAX, 0x204), /* value=0x0 */ 160 MFX(0xc0011001, "AMD_K7_APIC_CLUSTER_ID", AmdK7ClusterIdMaybe, AmdK7ClusterIdMaybe, 0, ~(uint64_t)UINT32_MAX, 0), /* value=0x0 */ 161 MFX(0xc0011004, "AMD_K8_CPUID_CTL_STD01", AmdK8CpuIdCtlStd01hEdcx, AmdK8CpuIdCtlStd01hEdcx, 0, ~(uint64_t)UINT32_MAX, 0), /* value=0x78bfbff */ 162 MFX(0xc0011005, "AMD_K8_CPUID_CTL_EXT01", AmdK8CpuIdCtlExt01hEdcx, AmdK8CpuIdCtlExt01hEdcx, 0, ~(uint64_t)UINT32_MAX, [all...] |
H A D | Quad_Core_AMD_Opteron_2384.h | 80 MFX(0x00000174, "IA32_SYSENTER_CS", Ia32SysEnterCs, Ia32SysEnterCs, 0, ~(uint64_t)UINT32_MAX, 0), /* value=0x0 */ 81 MFX(0x00000175, "IA32_SYSENTER_ESP", Ia32SysEnterEsp, Ia32SysEnterEsp, 0, ~(uint64_t)UINT32_MAX, 0), /* value=0x0 */ 82 MFX(0x00000176, "IA32_SYSENTER_EIP", Ia32SysEnterEip, Ia32SysEnterEip, 0, ~(uint64_t)UINT32_MAX, 0), /* value=0x0 */ 125 MFX(0xc0000084, "AMD64_SYSCALL_FLAG_MASK", Amd64SyscallFlagMask, Amd64SyscallFlagMask, 0, ~(uint64_t)UINT32_MAX, 0), /* value=0x14700 */ 129 MFX(0xc0000103, "AMD64_TSC_AUX", Amd64TscAux, Amd64TscAux, 0, ~(uint64_t)UINT32_MAX, 0), /* value=0x0 */ 144 MFX(0xc0010022, "AMD_K8_MC_XCPT_REDIR", AmdK8McXcptRedir, AmdK8McXcptRedir, 0, ~(uint64_t)UINT32_MAX, 0), /* value=0x0 */ 150 MFX(0xc0010045, "AMD_K8_MC_CTL_MASK_1", AmdK8McCtlMaskN, AmdK8McCtlMaskN, 0x1, ~(uint64_t)UINT32_MAX, 0), /* value=0x80 */ 156 MFX(0xc0010054, "AMD_K8_SMI_ON_IO_TRAP_CTL_STS", AmdK8SmiOnIoTrapCtlSts, AmdK8SmiOnIoTrapCtlSts, 0, ~(uint64_t)UINT32_MAX, 0), /* value=0x0 */ 157 MFX(0xc0010055, "AMD_K8_INT_PENDING_MSG", AmdK8IntPendingMessage, AmdK8IntPendingMessage, 0, ~(uint64_t)UINT32_MAX, 0), /* value=0x0 */ 158 MFX(0xc0010056, "AMD_K8_SMI_TRIGGER_IO_CYCLE", AmdK8SmiTriggerIoCycle, AmdK8SmiTriggerIoCycle, 0, ~(uint64_t)UINT32_MAX, [all...] |
H A D | AMD_Phenom_II_X6_1100T.h | 83 MFX(0x00000174, "IA32_SYSENTER_CS", Ia32SysEnterCs, Ia32SysEnterCs, 0, ~(uint64_t)UINT32_MAX, 0), /* value=0x10 */ 84 MFX(0x00000175, "IA32_SYSENTER_ESP", Ia32SysEnterEsp, Ia32SysEnterEsp, 0, ~(uint64_t)UINT32_MAX, 0), /* value=0x0 */ 85 MFX(0x00000176, "IA32_SYSENTER_EIP", Ia32SysEnterEip, Ia32SysEnterEip, 0, ~(uint64_t)UINT32_MAX, 0), /* value=0x8174c700 */ 128 MFX(0xc0000084, "AMD64_SYSCALL_FLAG_MASK", Amd64SyscallFlagMask, Amd64SyscallFlagMask, 0, ~(uint64_t)UINT32_MAX, 0), /* value=0x3700 */ 132 MFX(0xc0000103, "AMD64_TSC_AUX", Amd64TscAux, Amd64TscAux, 0, ~(uint64_t)UINT32_MAX, 0), /* value=0x0 */ 148 MFX(0xc0010022, "AMD_K8_MC_XCPT_REDIR", AmdK8McXcptRedir, AmdK8McXcptRedir, 0, ~(uint64_t)UINT32_MAX, 0), /* value=0x0 */ 154 MFX(0xc0010045, "AMD_K8_MC_CTL_MASK_1", AmdK8McCtlMaskN, AmdK8McCtlMaskN, 0x1, ~(uint64_t)UINT32_MAX, 0), /* value=0x80 */ 160 MFX(0xc0010054, "AMD_K8_SMI_ON_IO_TRAP_CTL_STS", AmdK8SmiOnIoTrapCtlSts, AmdK8SmiOnIoTrapCtlSts, 0, ~(uint64_t)UINT32_MAX, 0), /* value=0x0 */ 161 MFX(0xc0010055, "AMD_K8_INT_PENDING_MSG", AmdK8IntPendingMessage, AmdK8IntPendingMessage, 0, ~(uint64_t)UINT32_MAX, 0), /* value=0x14000815 */ 162 MFX(0xc0010056, "AMD_K8_SMI_TRIGGER_IO_CYCLE", AmdK8SmiTriggerIoCycle, AmdK8SmiTriggerIoCycle, 0, ~(uint64_t)UINT32_MAX, [all...] |
H A D | AMD_Athlon_64_X2_Dual_Core_4200.h | 78 MFX(0x00000174, "IA32_SYSENTER_CS", Ia32SysEnterCs, Ia32SysEnterCs, 0, ~(uint64_t)UINT32_MAX, 0), /* value=0x10 */ 79 MFX(0x00000175, "IA32_SYSENTER_ESP", Ia32SysEnterEsp, Ia32SysEnterEsp, 0, ~(uint64_t)UINT32_MAX, 0), /* value=0x0 */ 80 MFX(0x00000176, "IA32_SYSENTER_EIP", Ia32SysEnterEip, Ia32SysEnterEip, 0, ~(uint64_t)UINT32_MAX, 0), /* value=0x8103ca80 */ 123 MFX(0xc0000084, "AMD64_SYSCALL_FLAG_MASK", Amd64SyscallFlagMask, Amd64SyscallFlagMask, 0, ~(uint64_t)UINT32_MAX, 0), /* value=0x3700 */ 127 MFX(0xc0000103, "AMD64_TSC_AUX", Amd64TscAux, Amd64TscAux, 0, ~(uint64_t)UINT32_MAX, 0), /* value=0x1 */ 150 MFX(0xc0010054, "AMD_K8_SMI_ON_IO_TRAP_CTL_STS", AmdK8SmiOnIoTrapCtlSts, AmdK8SmiOnIoTrapCtlSts, 0, ~(uint64_t)UINT32_MAX, UINT32_C(0xffff1f00)), /* value=0x0 */ 151 MFX(0xc0010055, "AMD_K8_INT_PENDING_MSG", AmdK8IntPendingMessage, AmdK8IntPendingMessage, 0, ~(uint64_t)UINT32_MAX, UINT32_C(0xe0000000)), /* value=0x3000000 */ 153 MFX(0xc0010111, "AMD_K8_SMM_BASE", AmdK8SmmBase, AmdK8SmmBase, 0, ~(uint64_t)UINT32_MAX, 0), /* value=0x98200 */ 156 MFX(0xc0010114, "AMD_K8_VM_CR", AmdK8VmCr, AmdK8VmCr, 0, ~(uint64_t)UINT32_MAX, UINT32_C(0xffffffe0)), /* value=0x0 */ 157 MFX(0xc0010115, "AMD_K8_IGNNE", AmdK8IgnNe, AmdK8IgnNe, 0, ~(uint64_t)UINT32_MAX, UINT32_ [all...] |
H A D | Intel_Pentium_4_3_00GHz.h | 33 { 0x00000004, 0x00000000, UINT32_MAX, 0x00004121, 0x01c0003f, 0x0000001f, 0x00000000, 0 }, 34 { 0x00000004, 0x00000001, UINT32_MAX, 0x00004143, 0x01c0103f, 0x000007ff, 0x00000000, 0 }, 35 { 0x00000004, 0x00000002, UINT32_MAX, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0 }, 65 MVX(0x00000039, "C2_UNK_0000_0039", 0x1, 0x1f, ~(uint64_t)UINT32_MAX), 67 MVX(0x00000080, "P4_UNK_0000_0080", 0, ~(uint64_t)UINT32_MAX, UINT32_MAX), 68 MFX(0x0000008b, "IA32_BIOS_SIGN_ID", Ia32BiosSignId, Ia32BiosSignId, 0, UINT32_MAX, 0), /* value=0x5`00000000 */ 71 MFX(0x00000174, "IA32_SYSENTER_CS", Ia32SysEnterCs, Ia32SysEnterCs, 0, ~(uint64_t)UINT32_MAX, 0), /* value=0x0 */ 180 MVX(0x000003a0, "P4_MSR_BSU_ESCR0", 0, ~(uint64_t)UINT32_MAX, UINT32_C(0x80000000)), 181 MVX(0x000003a1, "P4_MSR_BSU_ESCR1", 0, ~(uint64_t)UINT32_MAX, UINT32_ [all...] |
H A D | AMD_FX_8150_Eight_Core.h | 42 { 0x0000000d, 0x00000000, UINT32_MAX, 0x00000007, 0x00000340, 0x000003c0, 0x40000000, 0 }, 43 { 0x0000000d, 0x00000001, UINT32_MAX, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0 }, 73 { 0x8000001d, 0x00000000, UINT32_MAX, 0x00000121, 0x00c0003f, 0x0000003f, 0x00000000, 0 }, 74 { 0x8000001d, 0x00000001, UINT32_MAX, 0x00004122, 0x0040003f, 0x000001ff, 0x00000000, 0 }, 75 { 0x8000001d, 0x00000002, UINT32_MAX, 0x00004143, 0x03c0003f, 0x000007ff, 0x00000001, 0 }, 76 { 0x8000001d, 0x00000003, UINT32_MAX, 0x0001c163, 0x0fc0003f, 0x000007ff, 0x00000001, 0 }, 77 { 0x8000001d, 0x00000004, UINT32_MAX, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0 }, 98 MFX(0x00000174, "IA32_SYSENTER_CS", Ia32SysEnterCs, Ia32SysEnterCs, 0, ~(uint64_t)UINT32_MAX, 0), /* value=0x0 */ 99 MFX(0x00000175, "IA32_SYSENTER_ESP", Ia32SysEnterEsp, Ia32SysEnterEsp, 0, ~(uint64_t)UINT32_MAX, 0), /* value=0x0 */ 100 MFX(0x00000176, "IA32_SYSENTER_EIP", Ia32SysEnterEip, Ia32SysEnterEip, 0, ~(uint64_t)UINT32_MAX, [all...] |
H A D | Intel_Core_i7_3960X.h | 33 { 0x00000004, 0x00000000, UINT32_MAX, 0x3c004121, 0x01c0003f, 0x0000003f, 0x00000000, 0 }, 34 { 0x00000004, 0x00000001, UINT32_MAX, 0x3c004122, 0x01c0003f, 0x0000003f, 0x00000000, 0 }, 35 { 0x00000004, 0x00000002, UINT32_MAX, 0x3c004143, 0x01c0003f, 0x000001ff, 0x00000000, 0 }, 36 { 0x00000004, 0x00000003, UINT32_MAX, 0x3c07c163, 0x04c0003f, 0x00002fff, 0x00000006, 0 }, 37 { 0x00000004, 0x00000004, UINT32_MAX, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0 }, 44 { 0x0000000b, 0x00000000, UINT32_MAX, 0x00000001, 0x00000002, 0x00000100, 0x00000002, 0 | CPUMCPUIDLEAF_F_INTEL_TOPOLOGY_SUBLEAVES | CPUMCPUIDLEAF_F_CONTAINS_APIC_ID }, 45 { 0x0000000b, 0x00000001, UINT32_MAX, 0x00000005, 0x0000000c, 0x00000201, 0x00000002, 0 | CPUMCPUIDLEAF_F_INTEL_TOPOLOGY_SUBLEAVES | CPUMCPUIDLEAF_F_CONTAINS_APIC_ID }, 46 { 0x0000000b, 0x00000002, UINT32_MAX, 0x00000000, 0x00000000, 0x00000002, 0x00000002, 0 | CPUMCPUIDLEAF_F_INTEL_TOPOLOGY_SUBLEAVES | CPUMCPUIDLEAF_F_CONTAINS_APIC_ID }, 48 { 0x0000000d, 0x00000000, UINT32_MAX, 0x00000007, 0x00000340, 0x00000340, 0x00000000, 0 }, 49 { 0x0000000d, 0x00000001, UINT32_MAX, [all...] |
/vbox/src/VBox/Runtime/r0drv/generic/ |
H A D | threadctxhooks-r0drv-generic.cpp | 47 return UINT32_MAX; 55 return UINT32_MAX;
|
/vbox/src/VBox/Runtime/include/internal/ |
H A D | filesystem.h | 48 #define RTFILESYSTEM_MATCH_SCORE_SUPPORTED UINT32_MAX
|
/vbox/src/VBox/Runtime/generic/ |
H A D | mempool-generic.cpp | 109 Assert((pEntry)->cRefs < UINT32_MAX / 2); \ 179 Assert(pFree->cRefs > 0 && pFree->cRefs < UINT32_MAX / 2); 185 pFree->cRefs = UINT32_MAX - 3; 363 RTMEMPOOL_VALID_ENTRY_RETURN_RC(pEntry, UINT32_MAX); 366 Assert(cRefs < UINT32_MAX / 2); 379 RTMEMPOOL_VALID_ENTRY_RETURN_RC(pEntry, UINT32_MAX); 383 AssertReturn(pEntry->cRefs > 0, UINT32_MAX); 386 Assert(cRefs < UINT32_MAX / 2); 390 pEntry->cRefs = UINT32_MAX - 2; 402 RTMEMPOOL_VALID_ENTRY_RETURN_RC(pEntry, UINT32_MAX); [all...] |
H A D | cdrom-generic.cpp | 46 AssertFailedReturn(UINT32_MAX); 52 AssertFailedReturn(UINT32_MAX);
|
/vbox/src/VBox/Additions/common/VBoxGuestLib/ |
H A D | VBoxGuestR3LibCpuHotPlug.cpp | 106 Req.idCpuCore = UINT32_MAX; 107 Req.idCpuPackage = UINT32_MAX;
|
/vbox/src/VBox/Runtime/r0drv/solaris/ |
H A D | dbgkrnlinfo-r0drv-solaris.c | 170 AssertPtrReturn(pThis, UINT32_MAX); 171 AssertMsgReturn(pThis->u32Magic == RTDBGKRNLINFO_MAGIC, ("%p: u32Magic=%RX32\n", pThis, pThis->u32Magic), UINT32_MAX); 184 AssertPtrReturn(pThis, UINT32_MAX); 185 AssertMsgReturn(pThis->u32Magic == RTDBGKRNLINFO_MAGIC, ("%p: u32Magic=%RX32\n", pThis, pThis->u32Magic), UINT32_MAX);
|
/vbox/src/VBox/VMM/VMMAll/ |
H A D | REMAll.cpp | 96 if (idxFree == UINT32_MAX) 105 } while (idxFree == UINT32_MAX); 219 idx != UINT32_MAX; 227 AssertRelease(pVM->rem.s.idxPendingList != UINT32_MAX); 232 AssertRelease(pVM->rem.s.idxPendingList == UINT32_MAX); 233 AssertRelease(pVM->rem.s.idxFreeList != UINT32_MAX);
|
/vbox/src/VBox/Runtime/common/crypto/ |
H A D | pkix-signature-core.cpp | 137 AssertPtrReturn(pThis, UINT32_MAX); 138 AssertReturn(pThis->u32Magic == RTCRPKIXSIGNATUREINT_MAGIC, UINT32_MAX); 151 AssertPtrReturn(pThis, UINT32_MAX); 152 AssertReturn(pThis->u32Magic == RTCRPKIXSIGNATUREINT_MAGIC, UINT32_MAX); 207 AssertReturn(cRefs != UINT32_MAX, VERR_INVALID_HANDLE); 261 AssertReturn(cRefs != UINT32_MAX, VERR_INVALID_HANDLE);
|
/vbox/src/VBox/Runtime/r0drv/linux/ |
H A D | threadctxhooks-r0drv-linux.c | 192 UINT32_MAX); 195 Assert(cRefs < UINT32_MAX / 2); 214 UINT32_MAX); 237 Assert(cRefs < UINT32_MAX / 2); 324 return UINT32_MAX; 332 return UINT32_MAX;
|
/vbox/src/VBox/Runtime/common/rand/ |
H A D | randadv.cpp | 133 return pThis->pfnGetU32(pThis, 0, UINT32_MAX) + INT32_MAX; 142 AssertPtrReturn(pThis, UINT32_MAX); 143 AssertReturn(pThis->u32Magic == RTRANDINT_MAGIC, UINT32_MAX); 155 AssertPtrReturn(pThis, UINT32_MAX); 156 AssertReturn(pThis->u32Magic == RTRANDINT_MAGIC, UINT32_MAX); 159 return pThis->pfnGetU32(pThis, 0, UINT32_MAX); 220 uint32_t u32 = pThis->pfnGetU32(pThis, 0, UINT32_MAX); 301 if (offLast == UINT32_MAX) 370 if (off <= UINT32_MAX) 373 return ( (uint64_t)pThis->pfnGetU32(pThis, 0, UINT32_MAX) [all...] |
/vbox/src/VBox/Runtime/common/dvm/ |
H A D | dvm.cpp | 220 AssertPtrReturn(pThis, UINT32_MAX); 221 AssertReturn(pThis->u32Magic == RTDVM_MAGIC, UINT32_MAX); 257 AssertPtrReturn(pThis, UINT32_MAX); 258 AssertReturn(pThis->u32Magic == RTDVM_MAGIC, UINT32_MAX); 406 AssertPtrReturn(pThis, UINT32_MAX); 407 AssertReturn(pThis->u32Magic == RTDVM_MAGIC, UINT32_MAX); 408 AssertReturn(pThis->hVolMgrFmt != NIL_RTDVMFMT, UINT32_MAX); 416 AssertPtrReturn(pThis, UINT32_MAX); 417 AssertReturn(pThis->u32Magic == RTDVM_MAGIC, UINT32_MAX); 418 AssertReturn(pThis->hVolMgrFmt != NIL_RTDVMFMT, UINT32_MAX); [all...] |