/illumos-gate/usr/src/uts/sun4u/sys/pci/ |
H A D | pcisch.h | 95 #define TOMATILLO_IOMMU_ERR (1ull << 24) 96 #define TOMATILLO_IOMMU_ERRSTS (3ull << 25) 97 #define TOMATILLO_IOMMU_ERR_ILLTSBTBW (1ull << 27) 98 #define TOMATILLO_IOMMU_ERR_BAD_VA (1ull << 28) 254 #define SCHIZO_PCI_CTRL_BUS_UNUSABLE (1ull << 63) 255 #define TOMATILLO_PCI_CTRL_PCI_DTO_ERR (1ull << 62) 256 #define TOMATILLO_PCI_CTRL_DTO_INT_EN (1ull << 61) 257 #define SCHIZO_PCI_CTRL_ERR_SLOT_LOCK (1ull << 51) 258 #define SCHIZO_PCI_CTRL_ERR_SLOT (7ull << 48) 260 #define SCHIZO_PCI_CTRL_PCI_TTO_ERR (1ull << 3 [all...] |
H A D | pci_iommu.h | 226 ((1ull << (iommu_p)->iommu_inst) & pci_dvma_debug_on) 228 ((1ull << (iommu_p)->iommu_inst) & pci_dvma_debug_off)
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/illumos-gate/usr/src/uts/sun4u/io/px/ |
H A D | px_err.h | 60 #define PX_ERR_EN_ALL -1ull 61 #define PX_ERR_MASK_NONE 0ull 63 #define LPU_INTR_ENABLE 0ull 64 #define LPU_INTR_DISABLE -1ull
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H A D | px_csr.h | 92 (1ull<<(off ## _ ## bit)))) 97 (1ull<<(off ## _ ## bit)))) 102 ~(1ull<<(off ## _ ## bit)))) 107 ~(1ull<<(off ## _ ## bit)))) 109 #define BIT_TST(reg, bitno) (reg & (1ull << bitno)) 110 #define BITMASK(bitno) (1ull << bitno)
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H A D | px_hlib.c | 46 * LPU_RESET should be set to 0ull during resume 101 * MMU_TTE_CACHE_INVALIDATE needs to be cleared. (-1ull) 125 * JBC_ERROR_STATUS_CLEAR needs to be cleared. (-1ull) 139 * UBC_ERROR_STATUS_CLEAR needs to be cleared. (-1ull) 228 CSR_XS(xbc_csr_base, JBC_CORE_AND_BLOCK_INTERRUPT_ENABLE, -1ull); 259 CSR_XS(xbc_csr_base, UBC_ERROR_LOG_ENABLE, -1ull); 266 CSR_XS(xbc_csr_base, UBC_ERROR_STATUS_CLEAR, -1ull); 374 val &= ~(1ull << TLU_CONTROL_NPWR_EN); 384 val |= (1ull << TLU_REMAIN_DETECT_QUIET); 595 val = (1ull << TLU_LINK_CONTROL_CLOC [all...] |
H A D | px_lib4u.h | 164 #define MMU_INVALID_TTE 0ull 179 #define MMU_FIRE_BYPASS_NONCACHE (1ull << 43) 184 #define MMU_OBERON_BYPASS_NONCACHE (1ull << 47) 205 #define MMU_TTE_V (1ull << 63) 206 #define MMU_TTE_W (1ull << 1) 207 #define MMU_TTE_RO (1ull << 62) /* Oberon Relaxed Ordering */
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/illumos-gate/usr/src/lib/libast/common/features/ |
H A D | limits.c | 95 uint64_t ull; local 127 ull = 0; 128 ull = ~ull; 264 if (ull == ul) 281 vll = ull; 292 vll = (uint64_t)(ull >> 1) + 1; 303 vll = (uint64_t)(ull >> 1);
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/illumos-gate/usr/src/uts/sun4v/io/ |
H A D | vgen_stats.c | 174 ldckp->ipackets64.value.ull = statsp->ipackets + 179 ldckp->opackets64.value.ull = statsp->opackets + 188 ldckp->rbytes64.value.ull = statsp->rbytes + 192 ldckp->obytes64.value.ull = statsp->obytes + 204 ldckp->tx_pri_packets.value.ull = statsp->tx_pri_packets; 205 ldckp->tx_pri_bytes.value.ull = statsp->tx_pri_bytes; 211 ldckp->rx_pri_packets.value.ull = statsp->rx_pri_packets; 212 ldckp->rx_pri_bytes.value.ull = statsp->rx_pri_bytes; 230 statsp->ipackets = ldckp->ipackets64.value.ull; 232 statsp->opackets = ldckp->opackets64.value.ull; [all...] |
/illumos-gate/usr/src/uts/sun4/io/px/ |
H A D | px_space.c | 74 hrtime_t px_intrpend_timeout = 5ull * NANOSEC; /* 5 seconds in nanoseconds */ 76 uint64_t px_perr_fatal = -1ull; 77 uint64_t px_serr_fatal = -1ull;
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H A D | px_mmu.h | 107 ((1ull << (mmu_p)->mmu_inst) & px_dvma_debug_on) 109 ((1ull << (mmu_p)->mmu_inst) & px_dvma_debug_off)
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/illumos-gate/usr/src/uts/common/crypto/io/ |
H A D | dca_kstat.c | 168 dca->dca_stats[i] = dkp->ds_algs[i].value.ull; 172 dkp->ds_mcr[i - 1].ds_submit.value.ull; 174 dkp->ds_mcr[i - 1].ds_flowctl.value.ull; 192 dkp->ds_algs[i].value.ull = dca->dca_stats[i]; 195 dkp->ds_mcr[i - 1].ds_submit.value.ull = 197 dkp->ds_mcr[i - 1].ds_flowctl.value.ull = 199 dkp->ds_mcr[i - 1].ds_lowater.value.ull = 201 dkp->ds_mcr[i - 1].ds_hiwater.value.ull = 203 dkp->ds_mcr[i - 1].ds_maxreqs.value.ull =
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/illumos-gate/usr/src/lib/sun_sas/common/ |
H A D | Sun_sasGetPhyStatistics.c | 219 psas->SecondsSinceLastReset = kname->value.ull; 223 psas->TxFrames = kname->value.ull; 227 psas->RxFrames = kname->value.ull; 231 psas->TxWords = kname->value.ull; 235 psas->RxWords = kname->value.ull; 239 psas->InvalidDwordCount = kname->value.ull; 243 psas->RunningDisparityErrorCount = kname->value.ull; 247 psas->LossofDwordSyncCount = kname->value.ull; 251 psas->PhyResetProblemCount = kname->value.ull;
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/illumos-gate/usr/src/uts/common/sys/ |
H A D | int_const.h | 66 * signedness. The suffix used for int64_t and uint64_t (ll and ull) 103 #define UINT64_C(c) __CONCAT__(c,ull) 117 #define UINTMAX_C(c) __CONCAT__(c,ull)
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/illumos-gate/usr/src/uts/sun4u/io/pci/ |
H A D | pci_space.c | 173 uint64_t pci_perr_enable = -1ull; 174 uint64_t pci_serr_enable = -1ull; 175 uint64_t pci_perr_fatal = -1ull; 176 uint64_t pci_serr_fatal = -1ull; 261 uint64_t xmits_error_intr_enable = -1ull;
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/illumos-gate/usr/src/cmd/cpio/ |
H A D | utils.c | 371 uint64_t ull; local 376 if ((str = get_ull_tok(str, &ull)) == NULL || *str != ' ') { 381 hi->holesdata_sz = (size_t)ull; 384 if (get_ull_tok(str, &ull) == NULL) 386 hi->orig_size = (off_t)ull; 400 uint64_t ull; local 413 if ((str = get_ull_tok(str, &ull)) == NULL) 415 hl->hl_data = (off_t)ull; 422 if ((str = get_ull_tok(str, &ull)) == NULL) 424 hl->hl_hole = (off_t)ull; [all...] |
/illumos-gate/usr/src/uts/common/io/sfe/ |
H A D | sfe_util.h | 444 #define GEM_TXFLAG_TCP_SHIFT 1ull 446 #define GEM_TXFLAG_UDP_SHIFT 2ull 448 #define GEM_TXFLAG_IPv4_SHIFT 3ull 450 #define GEM_TXFLAG_IPv6_SHIFT 4ull 455 #define GEM_TXFLAG_PRIVATE_SHIFT 8ull 458 #define GEM_TXFLAG_VID_SHIFT 16ull 462 #define GEM_TXFLAG_PRI_SHIFT 29ull 465 #define GEM_TXFLAG_VTAG_SHIFT 16ull 467 #define GEM_TXFLAG_HCKSTART_SHIFT 32ull 469 #define GEM_TXFLAG_HCKSTUFF_SHIFT 40ull [all...] |
/illumos-gate/usr/src/uts/sun4v/io/n2rng/ |
H A D | n2rng_kstat.c | 139 n2rng->n_stats[i] = dkp->ns_algs[i].value.ull; 155 dkp->ns_algs[i].value.ull = n2rng->n_stats[i]; 193 dkp->ns_rngbias[i][j].value.ull = 195 dkp->ns_rngentropy[i][j].value.ull =
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/illumos-gate/usr/src/cmd/dumpadm/ |
H A D | minfree.c | 80 minfree_write(const char *dir, unsigned long long ull) argument 85 int status = fprintf(fp, "%llu\n", ull);
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/illumos-gate/usr/src/uts/sun4v/sys/ |
H A D | niagara2regs.h | 71 #define CPC_PCR_HT (1ull << CPC_PCR_HT_SHIFT) 75 #define CPC_PCR_TOE0 (1ull << CPC_PCR_TOE0_SHIFT) 76 #define CPC_PCR_TOE1 (1ull << CPC_PCR_TOE1_SHIFT) 91 #define CPC_PCR_SAMPLE_MODE_MASK (1ull << CPC_PCR_SAMPLE_MODE_SHIFT) 97 #define CPC_PCR_HOLDOV0 (1ull << CPC_PCR_HOLDOV0_SHIFT) 98 #define CPC_PCR_HOLDOV1 (1ull << CPC_PCR_HOLDOV1_SHIFT)
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H A D | mmu.h | 150 #define MAX_NCTXS (1ull << MAX_NCTXS_BITS)
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/illumos-gate/usr/src/cmd/fm/modules/common/eversholt/ |
H A D | eft_mdb.c | 310 unsigned long long ull; local 315 ull = addr; 318 'l', MDB_OPT_UINT64, &ull, 325 if (mdb_vread(&ull, sizeof (ull), addr) != sizeof (ull)) { 331 if (ull == 0) 333 else if (ull >= TIMEVAL_EVENTUALLY) 335 else if (NOREMAINDER(ull, 1000000000ULL*60*60*24*365, val)) 337 else if (NOREMAINDER(ull, 100000000 [all...] |
H A D | iexpr.c | 124 return ((int)np->u.ull); 213 if (np2->u.ull > np1->u.ull) 215 else if (np1->u.ull > np2->u.ull)
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/illumos-gate/usr/src/uts/sun4u/starfire/os/ |
H A D | bbus_intr.c | 349 sgnblk_poll_time.cyt_when = 0ull; 350 sgnblk_poll_time.cyt_interval = sgnblk_poll_interval * 1000ull; 476 if (sgnblk_poll_time.cyt_interval > 0ull) 491 sgnblk_poll_time.cyt_when = 0ull; 492 sgnblk_poll_time.cyt_interval = new_interval * 1000ull;
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/illumos-gate/usr/src/uts/sun4v/cpu/ |
H A D | niagara.c | 141 hole_start = (caddr_t)((1ull << (va_bits - 1)) - (1ull << 32)); 142 hole_end = (caddr_t)((0ull - (1ull << (va_bits - 1))) + (1ull << 32));
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/illumos-gate/usr/src/uts/common/io/pciex/ |
H A D | pcieb.h | 148 #define PCIEB_ADDR_LIMIT_LO 0ull 149 #define PCIEB_ADDR_LIMIT_HI ((1ull << 40) - 1)
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