Searched refs:clearphys (Results 1 - 8 of 8) sorted by relevance
/illumos-gate/usr/src/uts/sun4u/cpu/ |
H A D | us3_cheetah_asm.s | 367 * clearphys - Pass in the physical memory address of the checkblock 378 clearphys(uint64_t paddr, int ecache_set_size, int ecache_linesize) 383 ENTRY(clearphys) function 428 SET_SIZE(clearphys)
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H A D | us3_cheetahplus_asm.s | 478 * clearphys - Pass in the physical memory address of the checkblock 489 clearphys(uint64_t paddr, int ecache_set_size, int ecache_linesize) 494 ENTRY(clearphys) function 549 SET_SIZE(clearphys)
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H A D | us3_jalapeno_asm.s | 890 * clearphys - Pass in the physical memory address of the checkblock 901 clearphys(uint64_t paddr, int ecache_set_size, int ecache_linesize) 906 ENTRY(clearphys) function 963 SET_SIZE(clearphys)
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H A D | spitfire_asm.s | 1617 * clearphys - Pass in the aligned physical memory address that you want 1626 clearphys(uint64_t paddr, int ecache_size, int ecache_linesize) 1632 ENTRY(clearphys) function 1760 SET_SIZE(clearphys)
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H A D | spitfire.c | 2309 clearphys(P2ALIGN(aflt->flt_addr, 64),
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H A D | us3_common.c | 3866 clearphys(aflt->flt_addr, ec_set_size, lsize);
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/illumos-gate/usr/src/uts/sun4u/sys/ |
H A D | machsystm.h | 344 extern void clearphys(uint64_t paddr, int ecache_size, int ecache_linesize);
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H A D | us3_module.h | 553 extern void clearphys(uint64_t paddr, int ecache_set_size, int ecache_linesize);
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