Searched defs:pwr_p (Results 1 - 6 of 6) sorted by relevance

/illumos-gate/usr/src/uts/sun4u/io/pci/
H A Dpci_pwr.c41 static void pci_pwr_update_comp(pci_pwr_t *pwr_p, pci_pwr_chld_t *p, int comp,
55 pci_pwr_get_info(pci_pwr_t *pwr_p, dev_info_t *dip) argument
59 ASSERT(PM_CAPABLE(pwr_p));
60 ASSERT(MUTEX_HELD(&pwr_p->pwr_mutex));
62 for (p = pwr_p->pwr_info; p != NULL; p = p->next) {
80 pci_pwr_create_info(pci_pwr_t *pwr_p, dev_info_t *dip) argument
84 ASSERT(PM_CAPABLE(pwr_p));
92 mutex_enter(&pwr_p->pwr_mutex);
100 pwr_p->pwr_fp++;
102 p->next = pwr_p
111 pci_pwr_rm_info(pci_pwr_t *pwr_p, dev_info_t *cdip) argument
161 pci_pwr_add_components(pci_pwr_t *pwr_p, dev_info_t *cdip, pci_pwr_chld_t *p) argument
210 pci_pwr_update_comp(pci_pwr_t *pwr_p, pci_pwr_chld_t *p, int comp, int lvl) argument
280 pci_pwr_new_lvl(pci_pwr_t *pwr_p) argument
373 pci_raise_power(pci_pwr_t *pwr_p, int current, int new, void *impl_arg, pm_bp_nexus_pwrup_t bpn) argument
398 pci_pwr_ops(pci_pwr_t *pwr_p, dev_info_t *dip, void *impl_arg, pm_bus_power_op_t op, void *arg, void *result) argument
532 pci_pwr_resume(dev_info_t *dip, pci_pwr_t *pwr_p) argument
591 pci_pwr_suspend(dev_info_t *dip, pci_pwr_t *pwr_p) argument
728 pci_pwr_change(pci_pwr_t *pwr_p, int current, int new) argument
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H A Dpci_pci.c1231 pci_pwr_current_lvl(pci_pwr_t *pwr_p) argument
1240 ddi_get_instance(pwr_p->pwr_dip));
1325 * not the translated bridge level stored in pwr_p->current_lvl
/illumos-gate/usr/src/uts/common/io/pciex/
H A Dpcie_pwr.c83 static int pcie_pwr_change(dev_info_t *dip, pcie_pwr_t *pwr_p, int new);
85 static int pwr_level_allowed(pcie_pwr_t *pwr_p);
87 pcie_pwr_t *pwr_p);
89 pcie_pwr_t *pwr_p);
90 static void pcie_pm_subrelease(dev_info_t *dip, pcie_pwr_t *pwr_p);
109 pcie_pwr_t *pwr_p = PCIE_NEXUS_PMINFO(dip); local
110 int *counters = pwr_p->pwr_counters;
111 int pmcaps = pwr_p->pwr_pmcaps;
125 mutex_enter(&pwr_p->pwr_lock);
127 ddi_driver_name(dip), ddi_get_instance(dip), pwr_p
189 pcie_pwr_change(dev_info_t *dip, pcie_pwr_t *pwr_p, int new) argument
268 pcie_pwr_t *pwr_p = PCIE_NEXUS_PMINFO(dip); local
478 pwr_level_allowed(pcie_pwr_t *pwr_p) argument
521 pcie_add_comps(dev_info_t *dip, dev_info_t *cdip, pcie_pwr_t *pwr_p) argument
558 pcie_remove_comps(dev_info_t *dip, dev_info_t *cdip, pcie_pwr_t *pwr_p) argument
604 pcie_pwr_t *pwr_p; local
644 pcie_pwr_t *pwr_p; local
671 pcie_pwr_t *pwr_p; local
718 pcie_pwr_t *pwr_p; local
731 pcie_pm_subrelease(dev_info_t *dip, pcie_pwr_t *pwr_p) argument
761 pcie_pwr_t *pwr_p; local
803 pcie_pwr_t *pwr_p; local
853 pcie_pwr_t *pwr_p = NULL; local
939 pcie_pwr_t *pwr_p = NULL; local
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H A Dpcieb.c136 static int pcieb_pwr_init_and_raise(dev_info_t *dip, pcie_pwr_t *pwr_p);
1542 pcie_pwr_t *pwr_p; local
1551 pwr_p = PCIE_NEXUS_PMINFO(dip);
1552 ASSERT(pwr_p);
1555 if (pci_config_setup(dip, &pwr_p->pwr_conf_hdl) != DDI_SUCCESS) {
1560 conf_hdl = pwr_p->pwr_conf_hdl;
1575 pwr_p->pwr_pmcsr_offset = cap_ptr + PCI_PMCSR;
1579 pwr_p->pwr_pmcaps |= PCIE_SUPPORTS_D1;
1583 pwr_p->pwr_pmcaps |= PCIE_SUPPORTS_D2;
1589 if (pwr_p
1614 pcie_pwr_t *pwr_p; local
1629 pcieb_pwr_init_and_raise(dev_info_t *dip, pcie_pwr_t *pwr_p) argument
1692 pcie_pwr_t *pwr_p; local
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/illumos-gate/usr/src/uts/sun4/io/px/
H A Dpx.c612 pcie_pwr_t *pwr_p; local
618 pwr_p = PCIE_NEXUS_PMINFO(dip);
619 ASSERT(pwr_p);
634 pwr_p->pwr_func_lvl = PM_LEVEL_D0;
/illumos-gate/usr/src/uts/sun4u/io/px/
H A Dpx_lib4u.c1872 pcie_pwr_t *pwr_p; local
1881 !(pwr_p = PCIE_NEXUS_PMINFO(px_p->px_dip)))
1884 mutex_enter(&pwr_p->pwr_lock);
1965 pwr_p->pwr_link_lvl = PM_LEVEL_L3;
1968 mutex_exit(&pwr_p->pwr_lock);
2001 pcie_pwr_t *pwr_p; local
2005 !(pwr_p = PCIE_NEXUS_PMINFO(px_p->px_dip)))
2013 return (pwr_p->pwr_link_lvl == PM_LEVEL_L3 ? DDI_SUCCESS : DDI_FAILURE);
2019 pcie_pwr_t *pwr_p; local
2027 !(pwr_p
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