Searched refs:pu64Base (Results 1 - 4 of 4) sorted by relevance
| /vbox/src/VBox/VMM/VMMAll/ |
| H A D | PDMAll.cpp | 261 * @param pu64Base Where to store the APIC base.
263 VMMDECL(int) PDMApicGetBase(PVMCPU pVCpu, uint64_t *pu64Base) argument
270 *pu64Base = pVM->pdm.s.Apic.CTX_SUFF(pfnGetBase)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns), pVCpu->idCpu);
274 *pu64Base = 0;
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| /vbox/include/VBox/vmm/ |
| H A D | pdmapi.h | 51 VMMDECL(int) PDMApicGetBase(PVMCPU pVCpu, uint64_t *pu64Base);
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| H A D | dbgf.h | 1473 VMMR3DECL(int) DBGFR3RegCpuQueryXdtr(PUVM pUVM, VMCPUID idCpu, DBGFREG enmReg, uint64_t *pu64Base, uint16_t *pu16Limit);
1519 VMMR3DECL(int) DBGFR3RegNmQueryXdtr(PUVM pUVM, VMCPUID idDefCpu, const char *pszReg, uint64_t *pu64Base, uint16_t *pu16Limit);
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| /vbox/src/VBox/VMM/VMMR3/ |
| H A D | DBGFReg.cpp | 1711 * @param pu64Base Where to store the register base value.
1714 VMMR3DECL(int) DBGFR3RegNmQueryXdtr(PUVM pUVM, VMCPUID idDefCpu, const char *pszReg, uint64_t *pu64Base, uint32_t *pu32Limit)
1720 *pu64Base = Value.dtr.u64Base;
1725 *pu64Base = 0;
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