Searched refs:GDTR (Results 1 - 9 of 9) sorted by relevance

/vbox/src/VBox/Runtime/common/asm/
H A DASMGetGDTR.asm35 ; Gets the content of the GDTR CPU register.
36 ; @param pGdtr Where to store the GDTR contents.
H A DASMSetGDTR.asm35 ; Sets the content of the GDTR CPU register.
36 ; @param pGdtr Where to load the GDTR contents from.
/vbox/src/VBox/VMM/VMMR3/
H A DSELM.cpp441 * Update GDTR and selector.
796 * Get the GDTR and check if there is anything to do (there usually is).
798 VBOXGDTR GDTR; local
799 CPUMGetGuestGDTR(pVCpu, &GDTR);
800 if (GDTR.cbGdt < sizeof(X86DESC))
810 RTUINT cbEffLimit = GDTR.cbGdt;
812 int rc = PGMPhysSimpleReadGCPtr(pVCpu, pGDTE, GDTR.pGdt + sizeof(X86DESC), cbEffLimit + 1 - sizeof(X86DESC));
825 RTGCPTR GCPtrSrc = (RTGCPTR)GDTR.pGdt + sizeof(X86DESC);
850 AssertLogRelMsgFailed(("Couldn't read GDT at %016RX64, rc=%Rrc!\n", GDTR.pGdt, rc));
869 pVM->selm.s.cbEffGuestGdtLimit, cbEffLimit, GDTR
1783 VBOXGDTR GDTR; local
2599 VBOXGDTR GDTR; local
[all...]
H A DCPUMDbg.cpp1238 CPU_REG_RW_AS("gdtr", GDTR, DTR, gdtr, cpumR3RegGet_gdtr, cpumR3RegSet_gdtr, NULL, NULL ),
1366 CPU_REG_RW_AS("gdtr", GDTR, DTR, gdtr, cpumR3RegGet_gdtr, cpumR3RegSet_gdtr, NULL, NULL ),
/vbox/include/VBox/vmm/
H A Dhm_svm.h190 /** GDTR read. */
198 /** GDTR write. */
320 /** 7 Intercept reads of GDTR. */
328 /** 11 Intercept writes of GDTR. */
460 * SVM GDTR/IDTR type.
697 /** Offset 0x460 - Guest GDTR register. */
698 SVMGDTR GDTR; member in struct:SVMVMCB::__anon351
819 AssertCompileMemberOffset(SVMVMCB, guest.GDTR, 0x460);
/vbox/src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseLib/X64/
H A DThunk16.S316 lgdt 0x60(%rsp) # restore protected mode GDTR
H A DThunk16.asm301 lgdt fword ptr [rsp + 60h] ; restore protected mode GDTR
/vbox/src/VBox/VMM/VMMR0/
H A DHMR0A.asm298 add rax, qword [rsi + VMXRESTOREHOST.HostGdtr + 2] ; xAX <- descriptor offset + GDTR.pGdt.
1069 ; * Gets 64-bit GDTR and IDTR on darwin.
1070 ; * @param pGdtr Where to store the 64-bit GDTR.
H A DHMSVMR0.cpp1347 /* Guest GDTR. */
1350 pVmcb->guest.GDTR.u32Limit = pCtx->gdtr.cbGdt;
1351 pVmcb->guest.GDTR.u64Base = pCtx->gdtr.pGdt;
2026 pMixedCtx->gdtr.cbGdt = pVmcb->guest.GDTR.u32Limit;
2027 pMixedCtx->gdtr.pGdt = pVmcb->guest.GDTR.u64Base;
2815 Log4(("guest.GDTR.u32Limit %#RX32\n", pVmcb->guest.GDTR.u32Limit));
2816 Log4(("guest.GDTR.u64Base %#RX64\n", pVmcb->guest.GDTR.u64Base));

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