Searched refs:BMCR_RESET (Results 1 - 10 of 10) sorted by relevance

/vbox/src/VBox/Devices/PC/ipxe/src/drivers/net/
H A Dmii.c55 ( BMCR_RESET | BMCR_ANENABLE ) ) ) != 0 ) {
74 if ( bmcr & BMCR_RESET ) {
H A Db44.c527 err = b44_phy_write(bp, MII_BMCR, BMCR_RESET);
534 if (val & BMCR_RESET) {
H A Dsis190.c467 while ((val & BMCR_RESET) && (cnt < 100)) {
474 DBG("sis190: BMCR_RESET timeout\n");
1086 BMCR_ANENABLE | BMCR_ANRESTART | BMCR_RESET);
H A Dtlan.c1449 value = BMCR_LOOPBACK | BMCR_RESET;
1452 while (value & BMCR_RESET) {
H A Dforcedeth.c1205 miicontrol = BMCR_RESET | bmcr_setup;
1213 while ( miicontrol & BMCR_RESET ) {
H A Djme.c114 MII_BMCR, val | BMCR_RESET);
H A Dbnx2.c730 bnx2_write_phy(bp, MII_BMCR, BMCR_RESET);
737 if (!(reg & BMCR_RESET)) {
H A Dvia-velocity.h1536 #define BMCR_RESET 0x8000 // macro
/vbox/src/VBox/Devices/PC/ipxe/src/include/
H A Dmii.h50 #define BMCR_RESET 0x8000 /* Reset the DP83840 */ macro
/vbox/src/VBox/Devices/PC/ipxe/src/drivers/net/tg3/
H A Dtg3_phy.c277 /* OK, reset it, and poll the BMCR_RESET bit until it
280 phy_control = BMCR_RESET;
291 if ((phy_control & BMCR_RESET) == 0) {

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