Searched refs:VEX_OPCODE_0F (Results 1 - 1 of 1) sorted by relevance
/openjdk7/hotspot/src/cpu/x86/vm/ |
H A D | assembler_x86.hpp | 528 VEX_OPCODE_0F = 0x1, enumerator in enum:Assembler::VexOpcode 596 vex_prefix(src, nds_enc, dst_enc, pre, VEX_OPCODE_0F, false, vector256); 605 VexOpcode opc = VEX_OPCODE_0F) { 613 VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F, 617 VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F) { 627 simd_prefix(dst, nds, src, pre, VEX_OPCODE_0F, rex_w); 631 VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F, 646 VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F) { 654 return simd_prefix_and_encode(dst, nds, as_XMMRegister(src->encoding()), pre, VEX_OPCODE_0F, rex_w); 660 VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F) { 603 vex_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, VexSimdPrefix pre, bool vector256 = false, VexOpcode opc = VEX_OPCODE_0F) argument 616 simd_prefix(XMMRegister dst, Address src, VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F) argument 645 simd_prefix_and_encode(Register dst, XMMRegister src, VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F) argument 659 simd_prefix_and_encode_q(Register dst, XMMRegister src, VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F) argument [all...] |
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