Searched refs:pci_phys_mid (Results 1 - 25 of 35) sorted by relevance

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/illumos-gate/usr/src/uts/sun4/io/px/
H A Dpx_util.c152 rp->pci_phys_hi, rp->pci_phys_mid, rp->pci_phys_low,
190 rp->pci_phys_mid += assign_p->pci_phys_mid;
202 rp->pci_phys_hi, rp->pci_phys_mid, rp->pci_phys_low,
221 reg_begin = (uint64_t)px_rp->pci_phys_mid << 32 | px_rp->pci_phys_low;
H A Dpx_tools.c475 dev_regspec.pci_phys_mid = 0; /* Not used */
477 dev_regspec.pci_phys_mid = offset >> 32;
/illumos-gate/usr/src/uts/sun4u/montecarlo/io/
H A Dacebus.c349 rangep[i].pci_phys_mid, rangep[i].pci_phys_low);
470 pci_reg.pci_phys_mid,
518 rp->pci_phys_mid = rangep->pci_phys_mid;
532 rangep->pci_phys_mid,
986 er[0].pci_phys_mid = prp->pci_phys_mid;
1009 er[1].pci_phys_mid = prp->pci_phys_mid;
/illumos-gate/usr/src/uts/common/io/
H A Dbusra.c1050 ((uint64_t)(regs[i].pci_phys_mid) << 32) |
1359 range_base = ((uint64_t)(regs[i].pci_phys_mid) << 32) |
1387 newregs[j].pci_phys_mid =
1399 newregs[j].pci_phys_mid =
1521 range_base = ((uint64_t)(regs[i].pci_phys_mid) << 32) |
1601 newregs[j].pci_phys_mid =
1615 newregs[k].pci_phys_mid =
1641 newregs[j].pci_phys_mid = (uint32_t)(base >> 32);
1670 newregs[0].pci_phys_mid = (uint32_t)(base >> 32);
/illumos-gate/usr/src/uts/sun4u/opl/io/pcicmu/
H A Dpcmu_util.c150 rp->pci_phys_hi, rp->pci_phys_mid, rp->pci_phys_low,
158 if (rp->pci_phys_mid != 0 || rp->pci_size_hi != 0) {
179 rp->pci_phys_hi, rp->pci_phys_mid, rp->pci_phys_low,
/illumos-gate/usr/src/uts/sun4u/sys/
H A Dsbbcvar.h72 uint32_t pci_phys_mid; /* Parent mid rng addr */ member in struct:sbbc_pci_rangespec
/illumos-gate/usr/src/uts/sun4u/montecarlo/sys/
H A Dacebus.h116 uint32_t pci_phys_mid; /* Parent mid rng addr */ member in struct:ebus_pci_rangespec
/illumos-gate/usr/src/uts/intel/io/intel_nhm/
H A Dnhm_pci_cfg.c48 reg.pci_phys_mid = 0;
/illumos-gate/usr/src/uts/sun4/io/efcode/
H A Dfcpci.c564 p.pci_phys_mid = fc_cell2uint(fc_arg(cp, 2));
851 p.pci_phys_mid = p.pci_phys_low = 0;
983 p.pci_phys_mid = p.pci_phys_low = 0;
1350 config.pci_phys_mid = config.pci_phys_low = 0;
1410 phys_spec.pci_phys_mid = HIADDR(answer);
1426 phys_spec.pci_phys_mid);
1456 phys_spec.pci_phys_mid = HIADDR(answer);
1577 config.pci_phys_mid = config.pci_phys_low = 0;
1636 phys_spec.pci_phys_mid),
/illumos-gate/usr/src/uts/sun4u/io/pci/
H A Dpci_util.c164 rp->pci_phys_hi, rp->pci_phys_mid, rp->pci_phys_low,
171 if (rp->pci_phys_mid != 0 || rp->pci_size_hi != 0) {
202 rp->pci_phys_hi, rp->pci_phys_mid, rp->pci_phys_low,
/illumos-gate/usr/src/uts/intel/io/intel_nb5000/
H A Dnb_pci_cfg.c53 reg.pci_phys_mid = 0;
/illumos-gate/usr/src/uts/sun4/io/
H A Dpcicfg.c2000 reg[i].pci_phys_mid =
2158 reg[i].pci_phys_mid = PCICFG_HIADDR(answer);
2303 assigned[i].pci_phys_mid);
2777 pci_ap[i].pci_phys_mid) +
2782 pci_ap[i].pci_phys_mid) +
3235 addition.pci_phys_mid = 0;
3368 addition.pci_phys_mid = base_hi;
4357 p.pci_phys_mid = p.pci_phys_low = 0;
5432 reg.pci_phys_mid = reg.pci_size_hi = 0;
5773 reg[i].pci_phys_mid, re
[all...]
H A Debus.c950 rp->pci_regspec.pci_phys_mid,
/illumos-gate/usr/src/uts/common/os/
H A Dpcifm.c1259 ((uint64_t)drv_regp[rn].pci_phys_mid << 32)) &&
1262 ((uint64_t)drv_regp[rn].pci_phys_mid << 32) +
1284 ((uint64_t)drv_regp[rn].pci_phys_mid << 32)) &&
1287 ((uint64_t)drv_regp[rn].pci_phys_mid << 32) +
/illumos-gate/usr/src/uts/intel/io/hotplug/pcicfg/
H A Dpcicfg.c1902 reg[i].pci_phys_mid = PCICFG_HIADDR(mem_answer);
2070 reg[i].pci_phys_mid = PCICFG_HIADDR(answer);
2105 reg[i].pci_phys_mid = 0;
2231 assigned[i].pci_phys_mid);
2748 assigned[i].pci_phys_mid),
2760 mem_type, assigned[i].pci_phys_mid,
3062 addition.pci_phys_mid = 0;
3147 addition.pci_phys_mid = base_hi;
4925 pci_ap[i].pci_phys_mid) +
4931 pci_ap[i].pci_phys_mid)
[all...]
/illumos-gate/usr/src/uts/sparc/io/pciex/
H A Dpcieb_sparc.c410 reg_spec[rnum].pci_phys_mid = 0;
/illumos-gate/usr/src/uts/i86pc/io/
H A Disa.c448 pci_reg_p->pci_phys_mid = 0;
483 pci_reg_p->pci_phys_mid = 0;
/illumos-gate/usr/src/uts/sun4u/io/
H A Dsbbc.c920 rp->pci_phys_mid = rangep->pci_phys_mid;
H A Dpmubus.c615 pci_regp->pci_phys_mid = rangep->rng_parent_mid;
/illumos-gate/usr/src/uts/i86pc/io/pci/
H A Dpci.c516 if (pci_rp->pci_phys_mid != 0 ||
H A Dpci_common.c1019 pci_rp->pci_phys_mid = assigned_addr[i].pci_phys_mid;
/illumos-gate/usr/src/uts/sun4u/starcat/io/
H A Ddman_domain.c774 pci_csr_base = regbuf[0].pci_phys_mid & PCI_CONF_ADDR_MASK;
/illumos-gate/usr/src/uts/common/io/cardbus/
H A Dcardbus_cfg.c911 reg[i].pci_phys_mid = PCICFG_LOADDR(mem_answer);
925 reg[i].pci_phys_mid = 0;
1054 range.par_phys_mid = reg[i].pci_phys_mid;
2296 assigned[i].pci_phys_mid,
3396 addition.pci_phys_mid = (uint32_t)((base>>32) & 0xffffffff);
3565 addition.pci_phys_mid = 0;
/illumos-gate/usr/src/uts/i86pc/io/pciex/
H A Dnpe.c657 if (pci_rp->pci_phys_mid != 0 || pci_rp->pci_size_hi != 0)
/illumos-gate/usr/src/uts/common/sys/
H A Dpci.h1114 * pci_phys_mid cell: hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh
1140 uint_t pci_phys_mid; /* child's address, middle word */ member in struct:pci_phys_spec

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