Searched refs:instruction (Results 1 - 25 of 43) sorted by relevance

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/illumos-gate/usr/src/cmd/sgs/rtld/sparc/
H A Dboot_a.out.s53 * save instruction before the call
119 sethi %hi(M_SETHIG1), %o3 ! Get sethi instruction
121 st %o3, [%o0] ! Store instruction in plt[0]
124 sethi %hi(M_JMPL), %o3 ! Get jmpl instruction
126 or %o3, %o2, %o3 ! is or'ed into instruction
127 st %o3, [%o0 + 4] ! Store instruction in plt[1]
H A Dboot_elf.s61 * save instruction before the call.
169 sethi %hi(M_SAVESP64), %o0 ! Get save instruction
180 sethi %hi(M_CALL), %o4 ! Get sethi instruction
182 st %o4, [%i0] ! Store instruction in plt
184 sethi %hi(M_NOP), %o0 ! Generate nop instruction
185 st %o0, [%i0 + 4] ! Store instruction in plt[2]
187 st %i1, [%i0 + 8] ! Store instruction in plt[3]
423 sethi %hi(M_JMPL), %o3 ! Get jmpl instruction
425 or %o3, %o2, %o3 ! is or'ed into instruction
426 st %o3, [%o0 + 8] ! Store instruction i
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/illumos-gate/usr/src/lib/libc/sparc/gen/
H A Dladd.s51 nop ! delay instruction.
53 nop ! delay instruction.
H A Dlsub.s50 nop ! delay instruction.
52 nop ! delay instruction.
H A Dlshiftl.s48 nop ! delay instruction.
50 nop ! delay instruction.
/illumos-gate/usr/src/cmd/sgs/rtld/sparcv9/
H A Dboot_elf.s64 * save instruction before the call.
81 * PC-relative jumps, and the rdpc instruction is very slow.
98 * the jmpl instruction we're got here with inside .PLT1
211 sethi %hi(M_SAVE_SP176SP), %o0 ! Get save instruction
217 or %o4, %o2, %o4 ! or value into instruction
218 st %o4, [%i0 + 0x4] ! Store instruction in plt[1]
223 or %o4, %o2, %o4 ! or value into instruction
224 st %o4, [%i0 + 0x8] ! Store instruction in plt[2]
230 or %o4, %o2, %o4 ! or value into instruction
231 st %o4, [%i0 + 0xc] ! Store instruction i
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/illumos-gate/usr/src/uts/sun4u/starcat/ml/
H A Ddrmach.il.cpp90 ! NOTE: The rdpr instruction executes as a noop. It has no
147 ! Flushes instruction cache. Used by drmach_copy_rename()
148 ! after the rename step to ensure the instruction cache tags
/illumos-gate/usr/src/common/ficl/
H A Ddictionary.c205 ficlString name, ficlInstruction instruction, ficlInteger value)
208 (ficlPrimitive)instruction, FICL_WORD_DEFAULT);
217 ficlString name, ficlInstruction instruction, ficl2Integer value)
220 (ficlPrimitive)instruction, FICL_WORD_DEFAULT);
253 ficlString name, ficlInstruction instruction, ficlInteger value)
260 name, instruction, value);
262 word->code = (ficlPrimitive)instruction;
281 ficlInstruction instruction, ficl2Integer value)
299 word->code = (ficlPrimitive)instruction;
304 instruction, valu
204 ficlDictionaryAppendConstantInstruction(ficlDictionary *dictionary, ficlString name, ficlInstruction instruction, ficlInteger value) argument
216 ficlDictionaryAppend2ConstantInstruction(ficlDictionary *dictionary, ficlString name, ficlInstruction instruction, ficl2Integer value) argument
252 ficlDictionarySetConstantInstruction(ficlDictionary *dictionary, ficlString name, ficlInstruction instruction, ficlInteger value) argument
280 ficlDictionarySet2ConstantInstruction(ficlDictionary *dictionary, ficlString s, ficlInstruction instruction, ficl2Integer value) argument
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H A Dprimitives.c220 * This function simply pops the previous instruction
2376 ficlInstruction instruction; local
2380 instruction =
2387 instruction = (isDouble) ? ficlInstructionGet2Local0 :
2391 instruction = ficlInstructionGetLocal1;
2394 instruction =
2400 ficlDictionaryAppendUnsigned(dictionary, instruction);
2474 ficlInstruction instruction; local
2490 instruction = ficlInstructionToF2LocalParen;
2493 instruction
2563 ficlInstruction instruction = 0; local
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H A Dvm.c255 ficlInstruction instruction; local
284 instruction = (ficlInstruction)((void *)fw);
286 instruction = *ip++;
287 fw = (ficlWord *)instruction;
291 switch (instruction) {
294 "Error: NULL instruction executed!");
314 (++dataTop)->i = instruction;
335 (++dataTop)->i = ficlInstruction0 - instruction;
488 * the instruction stream.
1129 * This function simply pops the previous instruction
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H A Dficl.h926 typedef ficlWord **ficlIp; /* the VM's instruction pointer */
1001 ficlIp ip; /* instruction pointer */
1251 * param[0] is the instruction.
1252 * When compiled, Ficl will simply copy over the instruction,
1410 ficlString name, ficlInstruction instruction, ficlInteger value);
1413 ficlString name, ficlInstruction instruction, ficl2Integer value);
1435 ficlString name, ficlInstruction instruction, ficlInteger value);
1438 ficlString name, ficlInstruction instruction, ficl2Integer value);
1553 * address - the location of the breakpoint (address of the instruction that
/illumos-gate/usr/src/uts/i86pc/ml/
H A Damd64.il162 * Call the halt instruction. This will put the CPU to sleep until
167 * subsequent instruction...in this case: "hlt".
174 / execute the bsrw instruction
H A Dsyscall_asm.s463 * System call handler via the sysenter instruction
472 * Normally the lcall instruction into the call gate causes the processor
480 * the IF (interrupt enable) flag turned on. (The int instruction into the
517 * call, as %edx is used by the sysexit instruction.
532 * through the kernel with kmdb, we will eventually hit the instruction at
535 * simply add a jump over the instruction at sys_sysenter to make it
/illumos-gate/usr/src/common/bignum/i386/
H A Dbignum_i386_asm.s165 / the x86 32 X 32 -> 64 unsigned multiply instruction, MUL.
179 / Using the cpuid instruction directly would work equally
181 / cpuid instruction in the kernel, we use x86_featureset,
215 / Suitable only for x86 models that support SSE2 instruction set extensions
372 / Suitable only for x86 models that support SSE2 instruction set extensions
449 / Suitable only for x86 models that support SSE2 instruction set extensions
476 / Suitable only for x86 models that support SSE2 instruction set extensions
658 / Suitable only for x86 models that support SSE2 instruction set extensions
880 / Suitable only for x86 models that support SSE2 instruction set extensions
1116 / Uses x86 unsigned 32 X 32 -> 64 multiply instruction, MU
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/illumos-gate/usr/src/ucbcmd/sbcp/
H A Dsbcp.s119 ! %g6 return address (after trap instruction)
/illumos-gate/usr/src/uts/sun4u/io/
H A Denvctrl_targets.c615 ehc_write_tda8444(struct ehc_envcunit *ehcp, int byteaddress, int instruction, argument
623 ASSERT(instruction == 0xf || instruction == 0x0);
626 control = (instruction << 4) | subaddress;
/illumos-gate/usr/src/lib/libtnfctl/
H A Dprb_rtld.c138 * instruction, istep, put the breakpoint back ...
332 #error What is your breakpoint instruction?
337 * the target process, and saves the existing instruction.
372 * the target process, and replaces it with the original instruction.
/illumos-gate/usr/src/lib/libc/i386/gen/
H A Dmemcpy.s128 addl %eax,%esi / rep; smovl instruction will decrement
/illumos-gate/usr/src/uts/intel/ia32/ml/
H A Dfloat.s180 .byte 0xf, 0xae, 0xf8 / [sfence instruction]
193 .byte 0xf, 0xae, 0xe8 / [lfence instruction]
243 movzbq (%rbp), %rsi /* instruction byte */
300 * instruction pointer, last data pointer, and last opcode
301 * are saved by the fxsave instruction ONLY if the exception summary
306 * rather slow and so we issue an instruction sequence that
316 1: rep; ret /* use 2 byte return instruction when branch target */
358 1: rep; ret /* use 2 byte return instruction when branch target */
377 1: rep; ret /* use 2 byte return instruction when branch target */
/illumos-gate/usr/src/cmd/sgs/rtld.4.x/
H A Drtldlib.s80 iflush %o0 ! Flush instruction memory
/illumos-gate/usr/src/uts/sparc/dtrace/
H A Ddtrace_asm.s272 sll %o1, 2, %o1 ! Multiply by instruction size
/illumos-gate/usr/src/uts/sfmmu/ml/
H A Dsfmmu_asm.s1015 /* fixup sethi instruction */
1052 /* fixup sethi instruction */
1057 /* fixup sethi instruction */
1064 /* fixup or instruction */
1071 /* fixup or instruction */
1107 ld [%o0], %o3 ! %o3 = instruction to patch
1113 st %o3, [%o0] ! store updated instruction
1128 1: ldsw [%o0], %o2 ! load instruction to %o2
1138 st %o2, [%o0] ! write patched instruction
1430 st %o1, [%o0] ! nop 1st instruction
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/illumos-gate/usr/src/uts/sun4u/cpu/
H A Dcommon_asm.s38 * instead of "done" instruction to return back to the user mode. See
46 * guaranteed to be exactly one instruction, be careful of using
49 * Do not use any instruction that modifies condition codes as the
103 * branch instruction needs to go over SETL41() macro
129 * instruction only when there is carry (less frequent).
195 * The failure occurs only when the following instruction decodes to wr or
953 * For OPL platforms that support the "sleep" instruction, we
954 * conditionally (ifdef'ed) insert a "sleep" instruction in
957 * is alot of code duplication just to add one "sleep" instruction.
989 .word 0x81b01060 ! insert "sleep" instruction
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/illumos-gate/usr/src/common/crypto/sha2/amd64/
H A Dsha512-x86_64.pl16 # same instruction sequence used for both SHA-256 and SHA-512. In
33 # actually possible to noticeably improve overall ILP, instruction
246 / the address of the "next" instruction into the target register
/illumos-gate/usr/src/uts/sun4v/ml/
H A Dtrap_table.s60 * instead of "done" instruction to return back to the user mode. See
280 * handler will resume execution at the last instruction of the window
746 * illegal instruction trap
783 * trap instruction for V9 user trap handlers
1136 IMMU_EXCEPTION; /* 008 instruction access exception */
1137 ITSB_MISS; /* 009 instruction access MMU miss */
1140 ILLTRAP_INSTR; /* 010 illegal instruction */
1185 ITLB_MISS(tt0); /* 064 instruction access MMU miss */
1295 NOT; /* 008 instruction access exception */
1296 ITSB_MISS; /* 009 instruction acces
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