Searched refs:enable_addr (Results 1 - 8 of 8) sorted by relevance

/illumos-gate/usr/src/uts/common/io/ixgbe/core/
H A Dixgbe_vf.h130 u32 enable_addr);
H A Dixgbe_vf.c341 * @enable_addr: set flag that address is active
344 u32 enable_addr)
350 UNREFERENCED_3PARAMETER(vmdq, enable_addr, index);
343 ixgbe_set_rar_vf(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq, u32 enable_addr) argument
H A Dixgbe_common.h100 u32 enable_addr);
H A Dixgbe_api.h111 u32 enable_addr);
H A Dixgbe_api.c897 * @enable_addr: set flag that address is active
902 u32 enable_addr)
905 enable_addr), IXGBE_NOT_IMPLEMENTED);
901 ixgbe_set_rar(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq, u32 enable_addr) argument
H A Dixgbe_common.c2284 * @enable_addr: set flag that address is active
2289 u32 enable_addr)
2323 if (enable_addr != 0)
2288 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq, u32 enable_addr) argument
/illumos-gate/usr/src/uts/sun4u/io/px/
H A Dpx_err_impl.h67 * enable_addr interrupt enable register offset
83 uint32_t enable_addr; member in struct:px_err_reg_desc
H A Dpx_err.c752 CSR_XS(csr_base, reg_desc_p->enable_addr, 0);
754 CSR_XS(csr_base, reg_desc_p->enable_addr, intr_mask);
756 CSR_XR(csr_base, reg_desc_p->enable_addr));
775 CSR_XS(csr_base, reg_desc_p->enable_addr, val);

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