Searched refs:clearphys (Results 1 - 8 of 8) sorted by relevance

/illumos-gate/usr/src/uts/sun4u/cpu/
H A Dus3_cheetah_asm.s367 * clearphys - Pass in the physical memory address of the checkblock
378 clearphys(uint64_t paddr, int ecache_set_size, int ecache_linesize)
383 ENTRY(clearphys) function
428 SET_SIZE(clearphys)
H A Dus3_cheetahplus_asm.s478 * clearphys - Pass in the physical memory address of the checkblock
489 clearphys(uint64_t paddr, int ecache_set_size, int ecache_linesize)
494 ENTRY(clearphys) function
549 SET_SIZE(clearphys)
H A Dus3_jalapeno_asm.s890 * clearphys - Pass in the physical memory address of the checkblock
901 clearphys(uint64_t paddr, int ecache_set_size, int ecache_linesize)
906 ENTRY(clearphys) function
963 SET_SIZE(clearphys)
H A Dspitfire_asm.s1617 * clearphys - Pass in the aligned physical memory address that you want
1626 clearphys(uint64_t paddr, int ecache_size, int ecache_linesize)
1632 ENTRY(clearphys) function
1760 SET_SIZE(clearphys)
H A Dspitfire.c2309 clearphys(P2ALIGN(aflt->flt_addr, 64),
H A Dus3_common.c3866 clearphys(aflt->flt_addr, ec_set_size, lsize);
/illumos-gate/usr/src/uts/sun4u/sys/
H A Dmachsystm.h344 extern void clearphys(uint64_t paddr, int ecache_size, int ecache_linesize);
H A Dus3_module.h553 extern void clearphys(uint64_t paddr, int ecache_set_size, int ecache_linesize);

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