Searched refs:TXC_FZC_CNTL_REG_WRITE64 (Results 1 - 3 of 3) sorted by relevance

/illumos-gate/usr/src/uts/common/io/nxge/npi/
H A Dnpi_txc.c613 TXC_FZC_CNTL_REG_WRITE64(handle, TXC_PORT_DMA_ENABLE_REG, port,
664 TXC_FZC_CNTL_REG_WRITE64(handle, TXC_PORT_DMA_ENABLE_REG, port,
702 TXC_FZC_CNTL_REG_WRITE64(handle, TXC_PORT_DMA_ENABLE_REG, port,
893 TXC_FZC_CNTL_REG_WRITE64(handle, TXC_ROECC_ST_REG, port,
913 TXC_FZC_CNTL_REG_WRITE64(handle, TXC_RO_CTL_REG, port, ctl.value);
923 TXC_FZC_CNTL_REG_WRITE64(handle, TXC_ROECC_ST_REG, port, 0);
976 TXC_FZC_CNTL_REG_WRITE64(handle, TXC_SFECC_ST_REG, port,
995 TXC_FZC_CNTL_REG_WRITE64(handle, TXC_SFECC_ST_REG, port, 0);
H A Dnpi_txc.h79 #define TXC_FZC_CNTL_REG_WRITE64(handle, reg, port, data) \ macro
/illumos-gate/usr/src/uts/common/io/nxge/
H A Dnxge_txc.c450 TXC_FZC_CNTL_REG_WRITE64(handle, TXC_ROECC_CTL_REG,
484 TXC_FZC_CNTL_REG_WRITE64(handle, TXC_SFECC_CTL_REG, portn, 0);
547 TXC_FZC_CNTL_REG_WRITE64(nxgep->npi_handle, TXC_ROECC_CTL_REG,
566 TXC_FZC_CNTL_REG_WRITE64(nxgep->npi_handle, TXC_SFECC_CTL_REG,

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