Searched refs:MII_CONTROL (Results 1 - 21 of 21) sorted by relevance

/illumos-gate/usr/src/uts/common/io/nge/
H A Dnge_xmii.c211 control = nge_mii_get16(ngep, MII_CONTROL);
213 nge_mii_put16(ngep, MII_CONTROL, control);
216 control = nge_mii_get16(ngep, MII_CONTROL);
242 control = nge_mii_get16(ngep, MII_CONTROL);
244 nge_mii_put16(ngep, MII_CONTROL, control);
249 control = nge_mii_get16(ngep, MII_CONTROL);
465 nge_mii_put16(ngep, MII_CONTROL, control);
474 control = nge_mii_get16(ngep, MII_CONTROL);
476 nge_mii_put16(ngep, MII_CONTROL, control);
/illumos-gate/usr/src/uts/intel/io/dnet/
H A Ddnet_mii.c124 mac->mii_read(dip, phy, MII_CONTROL);
127 mac->mii_read(dip, phy, MII_CONTROL), status);
301 mac->mii_write(mac->mii_dip, phy, MII_CONTROL,
313 control = mac->mii_read(mac->mii_dip, phy, MII_CONTROL);
324 control = mac->mii_read(mac->mii_dip, phy, MII_CONTROL);
386 mac->mii_write(mac->mii_dip, phy, MII_CONTROL, phyd->control);
455 mac->mii_write(mac->mii_dip, phy, MII_CONTROL, phyd->control);
541 mac->mii_write(mac->mii_dip, phy, MII_CONTROL, phyd->control);
559 mac->mii_write(mac->mii_dip, phy, MII_CONTROL, phyd->control);
575 mac->mii_write(mac->mii_dip, phy, MII_CONTROL, phy
[all...]
/illumos-gate/usr/src/uts/common/io/atge/
H A Datge_mii.c198 atge_mii_write(atgep, phyaddr, MII_CONTROL, MII_CONTROL_RESET);
223 atge_mii_write(atgep, phyaddr, MII_CONTROL,
370 if (reg == MII_CONTROL) {
/illumos-gate/usr/src/uts/common/io/usbgem/
H A Dusbgem_mii.h43 #define MII_CONTROL 0 macro
H A Dusbgem.c1514 val = usbgem_mii_read(dp, MII_CONTROL, &err);
1527 usbgem_mii_write(dp, MII_CONTROL, 0, &err);
1532 val = usbgem_mii_read(dp, MII_CONTROL, &err);
1783 val = usbgem_mii_read(dp, MII_CONTROL, &err);
1834 val = usbgem_mii_read(dp, MII_CONTROL, &err);
1871 usbgem_mii_write(dp, MII_CONTROL, val, &err);
2068 usbgem_mii_write(dp, MII_CONTROL, MII_CONTROL_RESET, &err);
2084 val = usbgem_mii_read(dp, MII_CONTROL, &err) &
2092 usbgem_mii_write(dp, MII_CONTROL,
2230 usbgem_mii_write(dp, MII_CONTROL,
[all...]
/illumos-gate/usr/src/uts/common/sys/
H A Dmiiregs.h38 #define MII_CONTROL 0 macro
/illumos-gate/usr/src/uts/common/io/mii/
H A Dmii.c1086 PHY_CLR(ph, MII_CONTROL,
1092 PHY_SET(ph, MII_CONTROL, MII_CONTROL_RESET);
1111 if ((phy_read(ph, MII_CONTROL) & MII_CONTROL_RESET) == 0) {
1124 phy_write(ph, MII_CONTROL, MII_CONTROL_ISOLATE);
1204 phy_write(ph, MII_CONTROL, bmcr);
1266 PHY_SET(ph, MII_CONTROL, MII_CONTROL_PWRDN);
1355 phy_write(ph, MII_CONTROL, bmcr & ~(MII_CONTROL_RSAN));
1368 phy_write(ph, MII_CONTROL, bmcr);
1384 control = phy_read(ph, MII_CONTROL);
H A Dmii_marvell.c193 reg = phy_read(ph, MII_CONTROL);
195 phy_write(ph, MII_CONTROL, reg);
/illumos-gate/usr/src/grub/grub-0.97/netboot/
H A Dsis900.h239 MII_CONTROL = 0x0000, enumerator in enum:mii_registers
H A Dsis900.c863 if(sis900_mdio_read(phy_addr, MII_CONTROL) & MII_CNTL_FDX)
/illumos-gate/usr/src/uts/common/io/bge/
H A Dbge_mii.c252 bge_mii_put16(bgep, MII_CONTROL, MII_CONTROL_RESET);
255 control = bge_mii_get16(bgep, MII_CONTROL);
277 bge_mii_put16(bgep, MII_CONTROL, MII_CONTROL_PWRDN);
1090 bge_mii_put16(bgep, MII_CONTROL, control);
H A Dbge_kstats.c498 { MII_CONTROL, "mii_control" },
/illumos-gate/usr/src/uts/common/io/bfe/
H A Dbfe.c376 bfe_write_phy(bfe, MII_CONTROL, MII_CONTROL_RESET);
379 if (bfe_read_phy(bfe, MII_CONTROL) &
418 bfe_write_phy(bfe, MII_CONTROL, MII_CONTROL_PWRDN |
443 bfe_write_phy(bfe, MII_CONTROL, 0);
452 bfe_write_phy(bfe, MII_CONTROL, 0);
698 bfe_write_phy(bfe, MII_CONTROL, bmcr);
742 bmcr = bfe_read_phy(bfe, MII_CONTROL);
/illumos-gate/usr/src/uts/common/io/mxfe/
H A Dmxfe.c975 mxfe_miiwrite(mxfep, mxfep->mxfe_phyaddr, MII_CONTROL,
1314 mxfe_miiwrite(mxfep, phyaddr, MII_CONTROL, MII_CONTROL_RESET);
1321 if (mxfe_miiread(mxfep, phyaddr, MII_CONTROL) &
1336 bmcr = mxfe_miiread(mxfep, phyaddr, MII_CONTROL);
1424 mxfe_miiwrite(mxfep, phyaddr, MII_CONTROL, bmcr);
1491 bmcr = mxfe_miiread(mxfep, mxfep->mxfe_phyaddr, MII_CONTROL);
/illumos-gate/usr/src/uts/common/io/sfe/
H A Dsfe_util.c2294 val = gem_mii_read(dp, MII_CONTROL);
2305 gem_mii_write(dp, MII_CONTROL, 0);
2543 val = gem_mii_read(dp, MII_CONTROL);
2589 val = gem_mii_read(dp, MII_CONTROL);
2619 gem_mii_write(dp, MII_CONTROL, val);
2785 gem_mii_write(dp, MII_CONTROL, MII_CONTROL_RESET);
2798 val = gem_mii_read(dp, MII_CONTROL) &
2801 gem_mii_write(dp, MII_CONTROL,
2873 gem_mii_write(dp, MII_CONTROL, 0);
2895 gem_mii_write(dp, MII_CONTROL,
[all...]
/illumos-gate/usr/src/uts/common/io/rge/
H A Drge_chip.c360 control = rge_mii_get16(rgep, MII_CONTROL);
361 rge_mii_put16(rgep, MII_CONTROL, control | MII_CONTROL_RESET);
364 control = rge_mii_get16(rgep, MII_CONTROL);
574 rge_mii_put16(rgep, MII_CONTROL, control);
/illumos-gate/usr/src/uts/common/io/urf/
H A Durf_usbgem.c564 case MII_CONTROL:
623 case MII_CONTROL:
/illumos-gate/usr/src/uts/common/io/afe/
H A Dafe.c1253 case MII_CONTROL:
1350 case MII_CONTROL:
/illumos-gate/usr/src/uts/common/io/rtls/
H A Drtls.c1925 case MII_CONTROL:
1967 case MII_CONTROL:
/illumos-gate/usr/src/uts/common/io/vr/
H A Dvr.c2703 vr_phy_write(vrp, MII_CONTROL, vrp->chip.mii.control);
2727 vr_phy_read(vrp, MII_CONTROL, &vrp->chip.mii.control);
/illumos-gate/usr/src/uts/common/io/nxge/npi/
H A Dnpi_mac.c3294 case MII_CONTROL:
3373 case MII_CONTROL:

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