Searched refs:IGU_REG_SB_MASK_LSB (Results 1 - 4 of 4) sorted by relevance

/illumos-gate/usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/vf/basic_vf/
H A Dlm_vf.c524 REG_WR(PFDEV(pdev), IGU_REG_SB_MASK_LSB, 0); local
/illumos-gate/usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/vf/channel_vf/
H A Dlm_vf.c2941 REG_WR(PFDEV(pdev), IGU_REG_SB_MASK_LSB, 0); local
/illumos-gate/usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/
H A Dlm_hw_init_reset.c3530 REG_WR(pdev, IGU_REG_SB_MASK_LSB, 0);
/illumos-gate/usr/src/uts/common/io/bnxe/577xx/hsi/hw/include/
H A D57712_reg.h5320 #define IGU_REG_SB_MASK_LSB 0x130164UL //ACCESS:RW DataWidth:0x20 SPLIT:72 Description: 32 lsb of SB mask register. 0 - unmased. 1 - masked. The bits order is according to the vector number of each SB in that function. For PF bit 0 is the default SB. bits 31:16 are valid only for functions that appears in func_with_more_16_sb_0..7 registers. macro
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