Searched refs:DBG_IB (Results 1 - 9 of 9) sorted by relevance
| /illumos-gate/usr/src/uts/sun4/io/px/ |
| H A D | px_ib.c | 60 DBG(DBG_IB, dip, "px_ib_attach\n");
99 DBG(DBG_IB, dip, "px_ib_detach\n");
124 DBG(DBG_IB, px_p->px_dip,
129 DBG(DBG_IB, px_p->px_dip,
150 DBG(DBG_IB, ib_p->ib_px_p->px_dip, "px_ib_intr_disable: ino=%x\n", ino);
155 DBG(DBG_IB, ib_p->ib_px_p->px_dip,
215 DBG(DBG_IB, dip, "px_ib_intr_dist_en: ino=0x%x\n", ino);
218 DBG(DBG_IB, dip, "px_ib_intr_dist_en: "
225 DBG(DBG_IB, dip, "px_ib_intr_dist_en: px_intr_getvalid() "
234 DBG(DBG_IB, di
[all...] |
| H A D | px_debug.h | 77 /* 32 */ DBG_IB, enumerator in enum:__anon9730
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| H A D | px_intr.c | 1001 DBG(DBG_IB, dip,
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| /illumos-gate/usr/src/uts/sun4u/io/pci/ |
| H A D | pci_debug.c | 70 {DBG_IB, "ib"},
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| H A D | pci_ib.c | 122 DEBUG0(DBG_IB, dip, "ib_destroy\n");
163 DEBUG2(DBG_IB, pci_p->pci_dip,
869 DEBUG0(DBG_IB, ib_p->ib_pci_p->pci_dip,
908 DEBUG1(DBG_IB, dip, "ib_get_intr_target: ino %x\n", ino);
915 DEBUG1(DBG_IB, dip, "ib_get_intr_target: cpu_id %x\n", *cpu_id_p);
939 DEBUG2(DBG_IB, dip, "ib_set_intr_target: ino %x cpu_id %x\n",
947 DEBUG1(DBG_IB, dip, "ib_set_intr_target: orig mapreg value: 0x%llx\n",
959 DEBUG0(DBG_IB, dip, "Clearing intr_enabled...\n");
965 DEBUG0(DBG_IB, dip, "About to check for pending interrupts...\n");
968 DEBUG0(DBG_IB, di
[all...] |
| H A D | pcipsy.c | 530 DEBUG3(DBG_IB, dip, "pci_xlate_intr: bus=%x, dev=%x, intr=%x\n",
535 DEBUG1(DBG_IB, dip, "pci_xlate_intr: done ino=%x\n", intr);
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| /illumos-gate/usr/src/uts/sun4u/sys/pci/ |
| H A D | pci_debug.h | 76 #define DBG_IB (0x20ull << 32) macro
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| /illumos-gate/usr/src/uts/sun4u/io/px/ |
| H A D | px_hlib.c | 296 DBG(DBG_IB, NULL, "hvio_ib_init - IMU_ERROR_LOG_ENABLE: 0x%llx\n",
299 DBG(DBG_IB, NULL, "hvio_ib_init - IMU_INTERRUPT_ENABLE: 0x%llx\n",
302 DBG(DBG_IB, NULL, "hvio_ib_init - IMU_INTERRUPT_STATUS: 0x%llx\n",
305 DBG(DBG_IB, NULL, "hvio_ib_init - IMU_ERROR_STATUS_CLEAR: 0x%llx\n",
2051 DBG(DBG_IB, NULL, "ino %x is invalid\n", devino);
2250 DBG(DBG_IB, NULL,
2257 DBG(DBG_IB, NULL, "hvio_msiq_init: "
2413 DBG(DBG_IB, NULL, "hvio_msi_init: MSI_32_BIT_ADDRESS: 0x%llx\n",
2419 DBG(DBG_IB, NULL, "hvio_msi_init: MSI_64_BIT_ADDRESS: 0x%llx\n",
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| H A D | px_lib4u.c | 2161 DBG(DBG_IB, pxp->px_dip, "px_cb_intr_redist: CB not enabled, "
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Completed in 107 milliseconds