Searched refs:CSR_XR (Results 1 - 4 of 4) sorted by relevance

/illumos-gate/usr/src/uts/sun4u/io/px/
H A Dpx_hlib.c211 CSR_XR(xbc_csr_base, JBUS_PARITY_CONTROL));
223 CSR_XR(xbc_csr_base, JBC_FATAL_RESET_ENABLE));
231 CSR_XR(xbc_csr_base, JBC_CORE_AND_BLOCK_INTERRUPT_ENABLE));
237 CSR_XR(xbc_csr_base, JBC_ERROR_LOG_ENABLE));
240 CSR_XR(xbc_csr_base, JBC_INTERRUPT_ENABLE));
243 CSR_XR(xbc_csr_base, JBC_INTERRUPT_STATUS));
246 CSR_XR(xbc_csr_base, JBC_ERROR_STATUS_CLEAR));
261 CSR_XR(xbc_csr_base, UBC_ERROR_LOG_ENABLE));
268 CSR_XR(xbc_csr_base, UBC_ERROR_STATUS_CLEAR));
274 CSR_XR(xbc_csr_bas
[all...]
H A Dpx_err.c756 CSR_XR(csr_base, reg_desc_p->enable_addr));
758 CSR_XR(csr_base, reg_desc_p->status_addr));
760 CSR_XR(csr_base, reg_desc_p->clear_addr));
763 CSR_XR(csr_base, reg_desc_p->log_addr));
888 ss_p->err_status[reg_id] = CSR_XR(csr_base,
1186 memory_ue_log = CSR_XR(csr_base, UBC_MEMORY_UE_LOG);
1246 ubc_intr_status = CSR_XR(csr_base, UBC_INTERRUPT_STATUS);
1265 CSR_XR(csr_base, UBC_ERROR_LOG_ENABLE),
1267 CSR_XR(csr_base, UBC_INTERRUPT_ENABLE),
1270 CSR_XR(csr_bas
[all...]
H A Dpx_csr.h37 #define CSR_XR(base, off) \ macro
H A Dpx_lib4u.c1466 return (CSR_XR((caddr_t)pxu_p->px_address[PX_REG_XBC], JBUS_SCRATCH_1));
2392 imu_log_enable = CSR_XR(csr_base, IMU_ERROR_LOG_ENABLE);
2393 imu_intr_enable = CSR_XR(csr_base, IMU_INTERRUPT_ENABLE);
2669 *mps = CSR_XR(csr_base, TLU_DEVICE_CAPABILITIES) &
2692 dev_ctrl = CSR_XR(csr_base, TLU_DEVICE_CONTROL);

Completed in 86 milliseconds