/vbox/src/VBox/VMM/VMMAll/ |
H A D | TMAllVirtual.cpp | 227 PVMCPU pVCpuDst = &pVM->aCpus[pVM->tm.s.idTimerCpu]; 394 PVMCPU pVCpuDst = &pVM->aCpus[pVM->tm.s.idTimerCpu]; 482 PVMCPU pVCpuDst = &pVM->aCpus[pVM->tm.s.idTimerCpu]; 538 PVMCPU pVCpuDst = &pVM->aCpus[pVM->tm.s.idTimerCpu]; 708 PVMCPU pVCpuDst = &pVM->aCpus[pVM->tm.s.idTimerCpu];
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H A D | PGMAllGst.h | 642 PVMCPU pVCpu = &pVM->aCpus[i]; 666 PVMCPU pVCpu = &pVM->aCpus[i];
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H A D | PGMAllMap.cpp | 747 PVMCPU pVCpu = &pVM->aCpus[0]; 840 PVMCPU pVCpu = &pVM->aCpus[0];
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H A D | PDMAllCritSect.cpp | 711 Assert(&pVCpu->CTX_SUFF(pVM)->aCpus[pVCpu->idCpu] == pVCpu);
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/vbox/src/VBox/VMM/VMMR3/ |
H A D | HM.cpp | 596 PVMCPU pVCpu = &pVM->aCpus[i]; 612 PVMCPU pVCpu = &pVM->aCpus[i]; 861 PVMCPU pVCpu = &pVM->aCpus[i]; 904 PVMCPU pVCpu = &pVM->aCpus[i]; 1194 LogRel(("HM: VCPU%3d: MSR bitmap physaddr = %#RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysMsrBitmap)); 1195 LogRel(("HM: VCPU%3d: VMCS physaddr = %#RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysVmcs)); 1297 PVMCPU pVCpu = &pVM->aCpus[i]; 1527 PVMCPU pVCpu = &pVM->aCpus[i]; 1628 PVMCPU pVCpu = &pVM->aCpus[i]; NOREF(pVCpu); 1705 PVMCPU pVCpu = &pVM->aCpus[ [all...] |
H A D | VMEmt.cpp | 165 rc = VMMR3EmtRendezvousFF(pVM, &pVM->aCpus[idCpu]); 231 PVMCPU pVCpu = &pVM->aCpus[idCpu]; 1015 g_aHaltMethods[iHaldMethod].pfnNotifyCpuFF(&pUVM->aCpus[iCpu], fFlags); 1188 g_aHaltMethods[pUVM->vm.s.iHaltMethod].pfnNotifyCpuFF(&pUVM->aCpus[0], 0 /*fFlags*/); 1320 PVMCPU pVCpu = &pVM->aCpus[idCpu]; 1347 PVMCPU pVCpu = &pVM->aCpus[idCpu];
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H A D | DBGF.cpp | 141 AssertCompile(sizeof(pUVM->aCpus[0].dbgf.s) <= sizeof(pUVM->aCpus[0].dbgf.padding)); 410 PVMCPU pVCpu = &pVM->aCpus[0]; 1232 VMCPU_FF_SET(&pVM->aCpus[idCpu], VMCPU_FF_INTERRUPT_NMI);
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H A D | PDMDevMiscHlp.cpp | 64 PVMCPU pVCpu = &pVM->aCpus[0]; /* for PIC we always deliver to CPU 0, MP use APIC */ 82 PVMCPU pVCpu = &pVM->aCpus[0]; /* for PIC we always deliver to CPU 0, MP use APIC */ 186 PVMCPU pVCpu = &pVM->aCpus[idCpu]; 223 PVMCPU pVCpu = &pVM->aCpus[idCpu];
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H A D | VMMTests.cpp | 196 PVMCPU pVCpu = &pVM->aCpus[0]; 250 PVMCPU pVCpu = &pVM->aCpus[0]; 339 PVMCPU pVCpu = &pVM->aCpus[0]; 640 PVMCPU pVCpu = &pVM->aCpus[0];
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H A D | PGMSavedState.cpp | 2086 rc = SSMR3PutStruct(pSSM, &pVM->aCpus[idCpu].pgm.s, &s_aPGMCpuFields[0]); 3018 rc = SSMR3GetStruct(pSSM, &pVM->aCpus[i].pgm.s, &s_aPGMCpuFieldsPrePae[0]); 3020 rc = SSMR3GetStruct(pSSM, &pVM->aCpus[i].pgm.s, &s_aPGMCpuFields[0]); 3036 pVM->aCpus[0].pgm.s.fA20Enabled = pgmOld.fA20Enabled; 3037 pVM->aCpus[0].pgm.s.GCPhysA20Mask = pgmOld.GCPhysA20Mask; 3038 pVM->aCpus[0].pgm.s.enmGuestMode = pgmOld.enmGuestMode; 3052 SSMR3GetGCPhys(pSSM, &pVM->aCpus[0].pgm.s.GCPhysA20Mask); 3056 pVM->aCpus[0].pgm.s.fA20Enabled = !!u32; 3057 SSMR3GetUInt(pSSM, &pVM->aCpus[0].pgm.s.fSyncFlags); 3060 pVM->aCpus[ [all...] |
H A D | GIMHv.cpp | 636 VMMHypercallsDisable(&pVM->aCpus[i]); 696 VMMHypercallsEnable(&pVM->aCpus[i]);
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H A D | VMMSwitcher.cpp | 175 CPUMSetHyperIDTR(&pVM->aCpus[iCpu], uIdtr, 16*256 + iCpu); 202 CPUMSetHyperIDTR(&pVM->aCpus[iCpu], uIdtr, 16*256 + iCpu); 570 Assert(offCPUM < sizeof(pVM->aCpus[0].cpum)); 571 *uSrc.pu32 = (uint32_t)(VM_RC_ADDR(pVM, &pVM->aCpus[0].cpum) + offCPUM);
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H A D | EM.cpp | 109 AssertCompile(sizeof(pVM->aCpus[0].em.s.u.FatalLongJump) <= sizeof(pVM->aCpus[0].em.s.u.achPaddingFatalLongJump)); 170 PVMCPU pVCpu = &pVM->aCpus[i]; 465 PVMCPU pVCpu = &pVM->aCpus[i]; 503 EMR3ResetCpu(&pVM->aCpus[i]); 538 PVMCPU pVCpu = &pVM->aCpus[i]; 593 PVMCPU pVCpu = &pVM->aCpus[i];
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H A D | DBGFReg.cpp | 466 pUVM->aCpus[iInstance].dbgf.s.pGuestRegSet = pRegSet; 468 pUVM->aCpus[iInstance].dbgf.s.pHyperRegSet = pRegSet; 809 ? pUVM->aCpus[idCpu].dbgf.s.pGuestRegSet 810 : pUVM->aCpus[idCpu].dbgf.s.pHyperRegSet; 1021 PVMCPU pVCpu = &pUVM->pVM->aCpus[idCpu]; 1178 PCDBGFREGSET pSet = pUVM->aCpus[0].dbgf.s.pGuestRegSet;
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H A D | PDM.cpp | 824 PVMCPU pVCpu = &pVM->aCpus[idCpu]; 854 PVMCPU pVCpu = &pVM->aCpus[idCpu]; 872 PVMCPU pVCpu = &pVM->aCpus[idCpu]; 917 PVMCPU pVCpu = &pVM->aCpus[idCpu]; 1316 int rc = VMR3AsyncPdmNotificationWaitU(&pVM->pUVM->aCpus[0]); 1554 PDMR3ResetCpu(&pVM->aCpus[idCpu]);
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H A D | MMHyper.cpp | 150 AssertRelease(pVM->cbSelf == RT_UOFFSETOF(VM, aCpus[pVM->cCpus])); 158 pVM->aCpus[i].pVMRC = pVM->pVMRC; 366 pVM->aCpus[i].pVMRC = pVM->pVMRC;
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H A D | DBGFCoreWrite.cpp | 435 PCPUMCTX pCpuCtx = CPUMQueryGuestCtxPtr(&pVM->aCpus[iCpu]);
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H A D | PATMSSM.cpp | 1266 LogFlow(("Changing fLocalForcedActions fixup from %RRv to %RRv\n", uFixup, pVM->pVMRC + RT_OFFSETOF(VM, aCpus[0].fLocalForcedActions))); 1267 *pFixup = pVM->pVMRC + RT_OFFSETOF(VM, aCpus[0].fLocalForcedActions); 1314 *pFixup = pVM->pVMRC + RT_OFFSETOF(VM, aCpus[0].fLocalForcedActions); 1359 *pFixup = pVM->pVMRC + RT_OFFSETOF(VM, aCpus[0].fLocalForcedActions);
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H A D | DBGFBp.cpp | 78 PVMCPU pVCpu = &pVM->aCpus[idCpu];
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/vbox/include/VBox/vmm/ |
H A D | vm.h | 749 #define VM_ASSERT_EMT0(pVM) VMCPU_ASSERT_EMT(&(pVM)->aCpus[0]) 755 #define VM_ASSERT_EMT0_RETURN(pVM, rc) VMCPU_ASSERT_EMT_RETURN(&(pVM)->aCpus[0], (rc)) 1176 VMCPU aCpus[1]; member in struct:VM
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/vbox/src/VBox/VMM/testcase/ |
H A D | tstPDMAsyncCompletionStress.cpp | 587 RTTlsSet(pVM->pUVM->vm.s.idxTLS, &pVM->pUVM->aCpus[0]); 588 pVM->pUVM->aCpus[0].pUVM = pVM->pUVM; 589 pVM->pUVM->aCpus[0].vm.s.NativeThreadEMT = RTThreadNativeSelf();
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H A D | tstMMHyperHeap.cpp | 75 pVM->cbSelf = RT_UOFFSETOF(VM, aCpus[pVM->cCpus]);
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/vbox/src/VBox/VMM/VMMR0/ |
H A D | PDMR0Device.cpp | 439 PVMCPU pVCpu = &pVM->aCpus[0]; /* for PIC we always deliver to CPU 0, MP use APIC */ 464 PVMCPU pVCpu = &pVM->aCpus[0]; /* for PIC we always deliver to CPU 0, MP use APIC */ 516 PVMCPU pVCpu = &pVM->aCpus[idCpu]; 567 PVMCPU pVCpu = &pVM->aCpus[idCpu];
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H A D | HMR0.cpp | 1228 PVMCPU pVCpu = &pVM->aCpus[i]; 1285 HMCPU_CF_RESET_TO(&pVM->aCpus[i], HM_CHANGED_HOST_CONTEXT | HM_CHANGED_ALL_GUEST); 1531 PVMCPU pVCpu = &pVM->aCpus[0];
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/vbox/src/VBox/VMM/VMMRC/ |
H A D | PDMRCDevice.cpp | 421 PVMCPU pVCpu = &pVM->aCpus[0]; /* for PIC we always deliver to CPU 0, MP use APIC */ 446 PVMCPU pVCpu = &pVM->aCpus[0]; /* for PIC we always deliver to CPU 0, MP use APIC */ 498 PVMCPU pVCpu = &pVM->aCpus[idCpu]; 530 PVMCPU pVCpu = &pVM->aCpus[idCpu];
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