Searched refs:u32 (Results 51 - 75 of 234) sorted by relevance

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/illumos-gate/usr/src/uts/common/io/chxge/com/
H A Dtp.c45 static inline u32 pm_num_pages(u32 size, u32 pg_size)
47 u32 num = size / pg_size;
54 u32 num;
74 static void tp_cm_configure(adapter_t *adapter, u32 cm_size)
76 u32 mm_base = (cm_size >> 1);
77 u32 mm_sub_size = (cm_size >> 5);
93 u32 tr = t1_read_reg_4(adap, A_TP_TIMER_RESOLUTION);
100 u32 t
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H A Dmv88e1xxx.c43 static void mdio_set_bit(struct cphy *cphy, int reg, u32 bitval)
45 u32 val;
54 static void mdio_clear_bit(struct cphy *cphy, int reg, u32 bitval)
56 u32 val;
76 u32 ctl;
99 u32 elmer;
118 u32 elmer;
132 u32 elmer;
155 u32 ctl;
178 u32 data3
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H A Dmc5.c116 u32 lip[MC5_LIP_NUM_OF_ENTRIES];
127 static int mc5_cmd_write(adapter_t *adapter, u32 cmd)
180 static inline void dbgi_wr_addr3(adapter_t *adapter, u32 v1, u32 v2, u32 v3)
187 static inline void dbgi_wr_data3(adapter_t *adapter, u32 v1, u32 v2, u32 v3)
194 static inline void dbgi_rd_rsp3(adapter_t *adapter, u32 *v1, u32 *v
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H A Dixf1010.c159 u32 mac_base;
160 u32 index;
161 u32 version;
162 u32 ticks;
167 u32 val;
184 u32 val;
228 u32 addr_lo, addr_hi;
245 u32 addr_lo, addr_hi;
268 u32 val, new_mode;
270 u32 addr_l
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H A Dvsc7321.c52 u32 addr;
53 u32 data;
59 u32 mac_base;
60 u32 index;
61 u32 version;
66 static void vsc_read(adapter_t *adapter, u32 addr, u32 *val)
68 u32 status, vlo, vhi;
84 static void vsc_write(adapter_t *adapter, u32 addr, u32 dat
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H A Dmc4.h52 u32 *buf);
/illumos-gate/usr/src/uts/common/io/i40e/core/
H A Di40e_type.h87 #define I40E_HI_DWORD(x) ((u32)((((x) >> 16) >> 16) & 0xFFFFFFFF))
88 #define I40E_LO_DWORD(x) ((u32)((x) & 0xFFFFFFFF))
313 u32 switch_mode;
318 u32 management_mode;
319 u32 npar_enable;
320 u32 os2bmc;
321 u32 valid_functions;
331 u32 flex10_mode;
336 u32 flex10_status;
344 u32 fd_filters_guarantee
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H A Di40e_hmc.c54 u32 sd_index,
147 u32 pd_index,
155 u32 sd_idx, rel_pd_idx;
229 u32 idx)
235 u32 sd_idx, rel_pd_idx;
284 u32 idx)
313 u32 idx, bool is_pf)
333 u32 idx)
362 u32 idx, bool is_pf)
/illumos-gate/usr/src/uts/common/io/e1000api/
H A De1000_manage.c44 u8 e1000_calculate_checksum(u8 *buffer, u32 length)
46 u32 i;
72 u32 hicr;
113 u32 fwsm = E1000_READ_REG(hw, E1000_FWSM);
132 u32 *buffer = (u32 *)&hw->mng_cookie;
133 u32 offset;
204 *((u32 *) hdr + i));
228 u32 data = 0;
244 for (j = prev_bytes; j < sizeof(u32);
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H A De1000_manage.h48 u8 e1000_calculate_checksum(u8 *buffer, u32 length);
49 s32 e1000_host_interface_command(struct e1000_hw *hw, u8 *buffer, u32 length);
50 s32 e1000_load_firmware(struct e1000_hw *hw, u8 *buffer, u32 length);
H A De1000_mac.c40 static int e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index);
130 u8 E1000_UNUSEDARG *h, u32 E1000_UNUSEDARG a)
141 u32 E1000_UNUSEDARG a, u32 E1000_UNUSEDARG b)
152 u8 E1000_UNUSEDARG *h, u32 E1000_UNUSEDARG a)
163 u32 E1000_UNUSEDARG a)
181 u32 status = E1000_READ_REG(hw, E1000_STATUS);
281 u32 reg;
300 u32 status;
334 u32 offse
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H A De1000_nvm.h54 u32 pba_num_size);
55 s32 e1000_read_pba_length_generic(struct e1000_hw *hw, u32 *pba_num_size);
57 u32 eeprom_buf_size, u16 max_pba_block_size,
60 u32 eeprom_buf_size, struct e1000_pba *pba);
62 u32 eeprom_buf_size, u16 *pba_block_size);
/illumos-gate/usr/src/uts/common/io/ixgbe/core/
H A Dixgbe_mbx.h140 s32 ixgbe_read_mbx(struct ixgbe_hw *, u32 *, u16, u16);
141 s32 ixgbe_write_mbx(struct ixgbe_hw *, u32 *, u16, u16);
142 s32 ixgbe_read_posted_mbx(struct ixgbe_hw *, u32 *, u16, u16);
143 s32 ixgbe_write_posted_mbx(struct ixgbe_hw *, u32 *, u16, u16);
H A Dixgbe_api.c40 static const u32 ixgbe_mvals_base[IXGBE_MVALS_IDX_LIMIT] = {
44 static const u32 ixgbe_mvals_X540[IXGBE_MVALS_IDX_LIMIT] = {
48 static const u32 ixgbe_mvals_X550[IXGBE_MVALS_IDX_LIMIT] = {
52 static const u32 ixgbe_mvals_X550EM_x[IXGBE_MVALS_IDX_LIMIT] = {
413 u32 ixgbe_get_num_of_tx_queues(struct ixgbe_hw *hw)
424 u32 ixgbe_get_num_of_rx_queues(struct ixgbe_hw *hw)
452 s32 ixgbe_read_pba_string(struct ixgbe_hw *hw, u8 *pba_num, u32 pba_num_size)
464 s32 ixgbe_read_pba_num(struct ixgbe_hw *hw, u32 *pba_num)
530 s32 ixgbe_read_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_typ
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H A Dixgbe_vf.c98 u32 vfsrrctl;
99 u32 vfdca_rxctrl;
100 u32 vfdca_txctrl;
178 u32 timeout = IXGBE_VF_INIT_TIMEOUT;
180 u32 msgbuf[IXGBE_VF_PERMADDR_MSG_LEN];
249 u32 reg_val;
298 u32 vector = 0;
325 u32 *msg, u16 size)
328 u32 retmsg[IXGBE_VFMAILBOX_SIZE];
343 s32 ixgbe_set_rar_vf(struct ixgbe_hw *hw, u32 inde
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H A Dixgbe_82599.c120 u32 esdp;
250 s32 prot_autoc_read_82599(struct ixgbe_hw *hw, bool *locked, u32 *reg_val)
279 s32 prot_autoc_write_82599(struct ixgbe_hw *hw, u32 autoc, bool locked)
416 u32 autoc = 0;
585 u32 autoc2_reg;
610 u32 autoc_reg;
611 u32 links_reg;
612 u32 i;
677 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
700 u32 esdp_re
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H A Dixgbe_x540.c210 u32 ctrl, i;
320 u32 ixgbe_get_supported_physical_layer_X540(struct ixgbe_hw *hw)
322 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
349 u32 eec;
672 u32 flup;
719 u32 i;
720 u32 reg;
749 s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask)
751 u32 swmask = mask & IXGBE_GSSR_NVM_PHY_MASK;
752 u32 fwmas
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H A Dixgbe_common.c49 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
50 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
73 u32 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
220 u32 reg = 0, reg_bp = 0;
379 u32 ctrl_ext;
424 u32 i;
425 u32 regval;
601 u32 pba_num_size)
680 if (pba_num_size < (((u32)length * 2) - 1)) {
710 s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_nu
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H A Dixgbe_dcb_82598.c121 u32 reg = 0;
122 u32 credit_refill = 0;
123 u32 credit_max = 0;
177 u32 reg, max_credits;
196 reg |= (u32)(bwg_id[i]) << IXGBE_TDTQ2TCCR_BWG_SHIFT;
221 u32 reg;
235 reg |= (u32)(max[i]) << IXGBE_TDPT2TCCR_MCL_SHIFT;
236 reg |= (u32)(bwg_id[i]) << IXGBE_TDPT2TCCR_BWG_SHIFT;
264 u32 fcrtl, reg;
316 u32 re
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H A Dixgbe_phy.h156 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr);
157 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id);
161 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
163 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
165 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
166 u32 device_type, u16 *phy_data);
167 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
168 u32 device_typ
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H A Dixgbe_dcb.h67 u32 capabilities; /* DCB capabilities */
131 u32 dcb_cfg_version; /* Not used...OS-specific? */
132 u32 link_speed; /* For bandwidth allocation validation purpose */
144 struct ixgbe_dcb_config *, u32, u8);
/illumos-gate/usr/src/uts/common/io/xge/hal/include/
H A Dxge-debug.h170 u32 module = XGE_COMPONENT_HAL_STATS;
189 u32 module = XGE_COMPONENT_HAL_INTERRUPT;
207 u32 module = XGE_COMPONENT_HAL_QUEUE;
227 u32 module = XGE_COMPONENT_HAL_MM;
246 u32 module = XGE_COMPONENT_HAL_CONFIG;
265 u32 module = XGE_COMPONENT_HAL_FIFO;
283 u32 module = XGE_COMPONENT_HAL_RING;
301 u32 module = XGE_COMPONENT_HAL_CHANNEL;
319 u32 module = XGE_COMPONENT_HAL_DEVICE;
337 u32 modul
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/illumos-gate/usr/src/grub/grub-0.97/netboot/
H A Deepro100.c108 typedef unsigned int u32; typedef
209 u32 tx_good_frames;
210 u32 tx_coll16_errs;
211 u32 tx_late_colls;
212 u32 tx_underruns;
213 u32 tx_lost_carrier;
214 u32 tx_deferred;
215 u32 tx_one_colls;
216 u32 tx_multi_colls;
217 u32 tx_total_coll
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/illumos-gate/usr/src/uts/common/kiconv/kiconv_ja/
H A Dkiconv_ja.c234 uint_t u32, /* UTF-32 to write */
243 if (u32 <= 0x7f) {
244 KICONV_JA_NPUT((uchar_t)(u32));
246 } else if (u32 <= 0x7ff) {
247 KICONV_JA_NPUT((uchar_t)((((u32)>>6) & 0x1f) | 0xc0));
248 KICONV_JA_NPUT((uchar_t)(((u32) & 0x3f) | 0x80));
250 } else if ((u32 >= 0xd800) && (u32 <= 0xdfff)) {
252 } else if (u32 <= 0xffff) {
253 KICONV_JA_NPUT((uchar_t)((((u32)>>1
233 write_unicode( uint_t u32, char **pop, size_t *poleft, int *errno) argument
328 uint_t u32; /* UTF-32 */ local
517 uint_t u32; /* UTF-32 */ local
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/illumos-gate/usr/src/uts/common/io/drm/
H A Dati_pcigart.c49 u32 *pci_gart = NULL, page_base;
70 pci_gart = (u32 *)entry->dmah_gart->vaddr;
88 page_base = (u32) entry->busaddr[pagenum];

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