/illumos-gate/usr/src/uts/common/io/ixgbe/core/ |
H A D | ixgbe_x550.c | 165 u32 retry; 238 u32 swfw_mask = hw->phy.phy_semaphore_mask; 314 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 357 static s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr, 358 u32 device_type, u16 *phy_data) 364 static s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr, 365 u32 device_type, u16 phy_data) 466 u32 reg, high_pri_tc; 514 u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb; 568 u32 re [all...] |
H A D | ixgbe_phy.c | 46 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl); 47 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl); 48 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data); 49 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl); 116 u32 swfw_mask = hw->phy.phy_semaphore_mask; 227 u32 swfw_mask = hw->phy.phy_semaphore_mask; 363 u32 phy_addr; 428 u32 mmngc; 451 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr) 475 u32 statu [all...] |
H A D | ixgbe_type.h | 634 u32 link_speed; 2785 #define __le32 u32 2794 #define __be32 u32 2970 u32 address; 2979 u32 address; 2999 u32 write_data; 3005 u32 read_data; 3157 typedef u32 ixgbe_autoneg_advertised; 3159 typedef u32 ixgbe_link_speed; 3173 typedef u32 ixgbe_physical_laye [all...] |
/illumos-gate/usr/src/grub/grub-0.97/netboot/ |
H A D | natsemi.c | 78 typedef uint32_t u32; typedef 166 u32 link; 167 volatile u32 cmdsts; 168 u32 bufptr; 169 u32 software_use; 188 static u32 SavedClkRun; 248 u32 tmp; 272 u32 newtmp = tmp & ~(0x03|0x100); 295 u32 chip_config = inl(ioaddr + ChipConfig); 507 txd.link = (u32) [all...] |
H A D | r8169.c | 59 typedef unsigned int u32; typedef 64 static u32 ioaddr; 259 u32 RxConfigMask; /* should clear the bits supported by this chip */ 272 u32 status; 273 u32 vlan_tag; 274 u32 buf_addr; 275 u32 buf_Haddr; 279 u32 status; 280 u32 vlan_tag; 281 u32 buf_add [all...] |
H A D | sis900.c | 203 u32 waittime = 0; 278 u32 rfcrSave; 279 u32 i; 450 u32 read_cmd = location | EEread; 459 u32 dataval = (read_cmd & (1 << i)) ? EEDI | EECS : EECS; 629 u32 status = TxRCMP | RxRCMP; 660 u32 rfcrSave; 670 u32 w; 672 w = (u32) *((u16 *)(nic->node_addr)+i); 698 txd.link = (u32) [all...] |
H A D | tlan.h | 47 typedef unsigned int u32; typedef 99 u32 flags; 416 inline u32 TLan_DioRead32(u16 base_addr, u16 internal_addr) 446 inline void TLan_DioWrite32(u16 base_addr, u16 internal_addr, u32 data) 485 inline u32 TLan_HashFunc(u8 * a) 501 inline u32 xor(u32 a, u32 b) 509 inline u32 TLan_HashFunc(u8 * a) 511 u32 has [all...] |
/illumos-gate/usr/src/uts/intel/io/drm/ |
H A D | r300_cmdbuf.c | 283 if (!RADEON_CHECK_OFFSET(dev_priv, (u32) values[i])) { 422 drm_radeon_kcmd_buffer_t *cmdbuf, u32 header) 426 u32 payload[MAX_ARRAY_PACKET]; 427 u32 narrays; 491 u32 *cmd = (u32 *)(uintptr_t)cmdbuf->buf; 498 u32 offset; 539 u32 *cmd = (u32 *)(uintptr_t)cmdbuf->buf; 570 u32 heade [all...] |
H A D | i915_irq.c | 43 #define MAX_NOPID ((u32)~0) 66 igdng_enable_irq(drm_i915_private_t *dev_priv, u32 mask, int gfx_irq) 81 igdng_disable_irq(drm_i915_private_t *dev_priv, u32 mask, int gfx_irq) 96 igdng_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask) 107 igdng_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask) 151 u32 reg = i915_pipestat(pipe); 161 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask) 164 u32 reg = i915_pipestat(pipe); 193 u32 i915_get_vblank_counter(struct drm_device *dev, int pipe) 198 u32 high [all...] |
/illumos-gate/usr/src/uts/common/io/e1000api/ |
H A D | e1000_82575.c | 60 static s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, 65 u32 offset, u16 *data); 67 u32 offset, u16 data); 80 u32 offset, u16 data); 104 static void e1000_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value); 114 static void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl); 115 static void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl); 116 static s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data); 117 static bool e1000_get_i2c_data(u32 *i2cct [all...] |
H A D | e1000_ich8lan.c | 80 static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index); 81 static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index); 85 u32 mc_addr_count); 122 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank); 126 u32 offset, u8 *data); 127 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 129 static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset, 130 u32 *data); 132 u32 offset, u32 *dat [all...] |
H A D | e1000_80003es2lan.c | 46 u32 offset, 49 u32 offset, 66 static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset, 68 static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset, 143 u32 eecd = E1000_READ_REG(hw, E1000_EECD); 404 u32 swfw_sync; 405 u32 swmask = mask; 406 u32 fwmask = mask << 16; 451 u32 swfw_sync; 474 u32 offse [all...] |
H A D | e1000_mbx.c | 54 u32 E1000_UNUSEDARG *msg, 72 s32 e1000_read_mbx(struct e1000_hw *hw, u32 *msg, u16 size, u16 mbx_id) 98 s32 e1000_write_mbx(struct e1000_hw *hw, u32 *msg, u16 size, u16 mbx_id) 246 s32 e1000_read_posted_mbx(struct e1000_hw *hw, u32 *msg, u16 size, u16 mbx_id) 275 s32 e1000_write_posted_mbx(struct e1000_hw *hw, u32 *msg, u16 size, u16 mbx_id) 322 static u32 e1000_read_v2p_mailbox(struct e1000_hw *hw) 324 u32 v2p_mailbox = E1000_READ_REG(hw, E1000_V2PMAILBOX(0)); 340 static s32 e1000_check_for_bit_vf(struct e1000_hw *hw, u32 mask) 342 u32 v2p_mailbox = e1000_read_v2p_mailbox(hw); 457 static s32 e1000_write_mbx_vf(struct e1000_hw *hw, u32 *ms [all...] |
H A D | e1000_82571.c | 208 u32 eecd = E1000_READ_REG(hw, E1000_EECD); 289 u32 swsm = 0; 290 u32 swsm2 = 0; 491 phy->id = (u32)(phy_id << 16); 497 phy->id |= (u32)(phy_id); 498 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); 516 u32 swsm; 577 u32 swsm; 597 u32 extcnf_ctrl; 634 u32 extcnf_ctr [all...] |
H A D | e1000_api.c | 553 void e1000_write_vfta(struct e1000_hw *hw, u32 offset, u32 value) 569 u32 mc_addr_count) 847 int e1000_rar_set(struct e1000_hw *hw, u8 *addr, u32 index) 878 u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr) 946 * @itr: u32 indicating itr value 950 s32 e1000_set_obff_timer(struct e1000_hw *hw, u32 itr) 982 s32 e1000_read_phy_reg(struct e1000_hw *hw, u32 offset, u16 *data) 999 s32 e1000_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data) 1057 s32 e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offse [all...] |
H A D | e1000_i210.c | 90 u32 swfw_sync; 91 u32 swmask = mask; 92 u32 fwmask = mask << 16; 142 u32 swfw_sync; 164 u32 swsm; 325 u32 i, k, eewr = 0; 326 u32 attempts = 100000; 379 u32 invm_dword; 598 u32 eec = 0; 619 u32 flu [all...] |
/illumos-gate/usr/src/uts/common/io/cxgbe/common/ |
H A D | t4_hw.c | 45 t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask, 46 int polarity, int attempts, int d, u32 *valp) 52 u32 val = t4_read_reg(adapter, reg); 82 t4_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask, u32 val) 84 u32 v = t4_read_reg(adapter, addr) & ~mask; 104 unsigned int data_reg, u32 *vals, unsigned int nregs, 128 unsigned int data_reg, const u32 *vals, unsigned int nregs, 141 get_mbox_rpl(struct adapter *adap, __be64 *rpl, int nflit, u32 mbox_addr) 151 fw_asrt(struct adapter *adap, u32 mbox_add [all...] |
/illumos-gate/usr/src/uts/common/io/chxge/com/ |
H A D | ulp.c | 47 u32 pl_intr = t1_read_reg_4(ulp->adapter, A_PL_ENABLE); 66 u32 pl_intr = t1_read_reg_4(ulp->adapter, A_PL_ENABLE); 76 u32 cause = t1_read_reg_4(ulp->adapter, A_ULP_INT_CAUSE);
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H A D | cspi.c | 48 int t1_cspi_intr_status_read(struct pecspi *cspi, u32 *status)
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H A D | my3126.c | 73 u32 val; 76 u32 act_count; 134 u32 val; 220 u32 val;
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H A D | vsc7326.c | 44 u32 addr; 45 u32 data; 49 u32 index; 50 u32 ticks; 55 static void vsc_read(adapter_t *adapter, u32 addr, u32 *val) 57 u32 status, vlo, vhi; 83 static void vsc_write(adapter_t *adapter, u32 addr, u32 data) 97 u32 va [all...] |
H A D | mc3.c | 48 u32 en = t1_read_reg_4(mc3->adapter, A_PL_ENABLE); 65 u32 pl_intr = t1_read_reg_4(mc3->adapter, A_PL_ENABLE); 88 u32 old_en; 113 u32 cause; 182 static int wrreg_wait(adapter_t *adapter, unsigned int addr, u32 val) 197 u32 val; 328 static unsigned int __devinit mc3_calc_size(const adapter_t *adapter, u32 cfg)
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/illumos-gate/usr/src/uts/common/io/i40e/core/ |
H A D | i40e_lan_hmc.c | 71 u64 i40e_calculate_l2fpm_size(u32 txq_num, u32 rxq_num, 72 u32 fcoe_cntx_num, u32 fcoe_filt_num) 107 enum i40e_status_code i40e_init_lan_hmc(struct i40e_hw *hw, u32 txq_num, 108 u32 rxq_num, u32 fcoe_cntx_num, 109 u32 fcoe_filt_num) 114 u32 size_exp; 228 hw->hmc.sd_table.sd_cnt = (u32) [all...] |
/illumos-gate/usr/src/uts/common/io/bnxe/ |
H A D | bnxe_debug.c | 88 void elink_cb_dbg1(struct elink_dev * bp, char * fmt, u32 arg1) 105 void elink_cb_dbg2(struct elink_dev * bp, char * fmt, u32 arg1, u32 arg2) 122 void elink_cb_dbg3(struct elink_dev * bp, char * fmt, u32 arg1, u32 arg2, u32 arg3)
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/illumos-gate/usr/src/uts/common/io/drm/ |
H A D | drm_ioctl.c | 60 drm_unique_32_t u32; local 62 DRM_COPYFROM_WITH_RETURN(&u32, (void *)data, sizeof (u32)); 63 u1.unique_len = u32.unique_len; 64 u1.unique = (char __user *)(uintptr_t)u32.unique; 81 drm_unique_32_t u32; local 83 u32.unique_len = (uint32_t)u1.unique_len; 84 u32.unique = (caddr32_t)(uintptr_t)u1.unique; 85 DRM_COPYTO_WITH_RETURN((void *)data, &u32, sizeof (u32)); [all...] |