Searched refs:CPU (Results 76 - 100 of 299) sorted by relevance

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/illumos-gate/usr/src/grub/grub-0.97/
H A Dconfig.guess259 # covers most systems running today. This code pipes the CPU
260 # types through head -n 1, so we only detect the type of CPU 0.
520 echo romp-ibm-aix # uname -m gives an 8 hex-code CPU id
848 #undef CPU
852 CPU=mipsel
855 CPU=mips
857 CPU=
861 eval `$CC_FOR_BUILD -E $dummy.c 2>/dev/null | grep ^CPU=`
862 test x"${CPU}" != x && echo "${CPU}
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/illumos-gate/usr/src/uts/sun4v/cpu/
H A Dniagara.c72 * Hypervisor services information for the NIAGARA CPU module
108 * The setup common to all CPU modules is done in cpu_setup_common
117 * Turn on the missing bits supported by Niagara CPU in
180 * default to the CPU id in the absence of such information.
217 long *ptr = &(dummy[CPU->cpu_seqid & 0x03].val);
385 (CPU->cpu_id+1) * sizeof (niagara_mmustat_t)),
414 mmustatp = &((niagara_mmustat_t *)cpu_tstat_va)[CPU->cpu_id+1];
/illumos-gate/usr/src/uts/sun4v/promif/
H A Dpromif_stree.c297 thread_affinity_set(curthread, CPU->cpu_id);
388 thread_affinity_set(curthread, CPU->cpu_id);
428 thread_affinity_set(curthread, CPU->cpu_id);
/illumos-gate/usr/src/uts/common/disp/
H A Dcmt_policy.c77 if (self && bitset_in_set(&here->cmt_cpus_actv_set, CPU->cpu_seqid))
114 * cp is a hint CPU, against which CMT load balancing will be performed.
116 * Returns cp, or a CPU better than cp with respect to balancing
175 * have some CPU resources in the thread's
212 * Select an idle CPU from the target
/illumos-gate/usr/src/uts/common/sys/
H A Dstrft.h157 _hp->cpu_seqid = CPU->cpu_seqid; \
/illumos-gate/usr/src/uts/sun4u/sunfire/io/
H A Dsysctrl_quiesce.c123 CPUSET_DEL(others, CPU->cpu_id);
125 (uint64_t)(&sysctrl_gate[CPU->cpu_id]));
162 sysctrl_gate[CPU->cpu_id] = 1;
379 if (tp->t_state == TS_ONPROC && tp->t_cpu != CPU)
/illumos-gate/usr/src/uts/sun4v/os/
H A Dmach_mp_states.c43 * set_idle_cpu is called from idle() when a CPU becomes idle.
52 * unset_idle_cpu is called from idle() when a CPU is no longer idle.
61 * Stop a CPU based on its cpuid, using the cpu_stop hypervisor call.
62 * Since this requires that the hypervisor force a remote CPU to stop,
65 * timeout is used to determine when to give up waiting for the CPU to
68 * Attempts to stop a CPU already in the stopped or error state will
86 * Check the state of the CPU up front to see if an
99 * The HV API to stop a CPU is only supported in
118 * clock frequency of the current CPU.
121 cpu_stop_time_limit = cpunodes[CPU
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/illumos-gate/usr/src/uts/sun4u/cpu/
H A Dus3_cheetah.c184 CPU_STATS_ADDQ(CPU, sys, xcalls, shipped);
193 * CPUs, set "index" to the highest numbered CPU in
207 CPU_STATS_ADDQ(CPU, sys, xcalls, ncpuids);
390 * UCU,UCC > UE,EDU,WDU,CPU > CE,EDC,EMC,WDC,CPC > TO,BERR
432 /* UE, EDU:ST, EDU:BLD, WDU, CPU */
449 C_AFSR_CPU, "CPU ", ECC_C_TRAP, CPU_UE_ECACHE,
450 "CPU",
506 * Class 3: UE, EDU, EMU, WDU, CPU
521 * Class 2: UE, IVU, EDU, WDU, UCU, CPU
563 processor_info_t *pi = &(CPU
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H A Dus3_cheetahplus.c191 CPU_STATS_ADDQ(CPU, sys, xcalls, shipped);
200 * CPUs, set "index" to the highest numbered CPU in
214 CPU_STATS_ADDQ(CPU, sys, xcalls, ncpuids);
419 if (IS_PANTHER(cpunodes[CPU->cpu_id].implementation))
432 * AFSR -- UE, DUE, EDU, WDU, CPU
526 /* UE, EDU:ST, EDU:BLD, WDU, CPU */
559 C_AFSR_CPU, "CPU ", ECC_C_TRAP,
560 CPU_UE_ECACHE, "CPU",
654 * AFSR -- UE, DUE, EDU, EMU, WDU, CPU
683 * Class 2: UE, DUE, IVU, EDU, EMU, WDU, UCU, CPU
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/illumos-gate/usr/src/uts/sun4u/io/
H A Dtodstarcat.c262 return (cpunodes[CPU->cpu_id].clock_freq);
H A Dtodsg.c526 cpunodes[CPU->cpu_id].clock_freq/1000000);
528 return (cpunodes[CPU->cpu_id].clock_freq);
/illumos-gate/usr/src/uts/intel/os/
H A Darch_kdi.c100 * CPU doesn't work until the GDT and gs/GSBASE have been set up.
123 * fake CPU set up by boot_kdi_tmpinit(). We're trying to restore the
131 CPU->cpu_m.mcpu_idt = idt;
/illumos-gate/usr/src/uts/i86pc/os/
H A Dmach_kdi.c52 gate_desc_t *idt = CPU->cpu_m.mcpu_idt;
H A Dmemscrub.c380 * the CPU-specific mapping of
386 * off CPU.
442 if (CPU->cpu_id == cpu_id &&
443 CPU->cpu_disp->disp_nrunnable == 0)
H A Dtrap.c493 CPU_STATS_ADDQ(CPU, sys, trap, 1);
949 * trap. Check for that case here. If this occurs on a CPU which
1300 * has been disabled on the CPU because it destroys segment
1302 * be a safe system call and retry it. If this occurs on a CPU
1565 if (CPU->cpu_runrun || curthread->t_schedflag & TS_ANYWAITQ)
1608 aston(CPU->cpu_dispthread);
1631 * resume: curthread->t_pri == -1 && CPU->dispthread
1632 * != CPU->thread
1639 if (CPU->cpu_dispthread != CPU
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/illumos-gate/usr/src/uts/common/tnf/
H A Dtrace_funcs.c209 if (sched->cpuid != CPU->cpu_id)
210 /* CPU information is invalid */
246 sched->cpuid = CPU->cpu_id;
/illumos-gate/usr/src/uts/sun4/io/
H A Dcbe.c77 cyclic_softint(CPU, CY_LOW_LEVEL);
84 cyclic_softint(CPU, CY_LOCK_LEVEL);
194 * simultaneously, we allocate a new set of inums for each CPU.
231 * If we're actually on a CPU which has apparently had %tick zeroed,
238 * We're the first CPU to be resumed. We want %tick
290 * If sys_tick_freq > NANOSEC (i.e. we're on a CPU with a clock rate
/illumos-gate/usr/src/uts/sun4/sys/
H A Dxc_impl.h93 cpuid = CPU->cpu_id; \
133 CPU_STATS_ADDQ(CPU, sys, xcalls, 1); \
/illumos-gate/usr/src/uts/sun4u/os/
H A Dmach_cpu_states.c93 * to the current CPU
210 * For platforms that use CPU signatures, we
233 CPU->cpu_m.in_prom = 1;
340 * For Platforms that use CPU signatures, we
354 * Disable further ECC errors from the CPU module and the bus nexus.
360 * Redirect all interrupts to the current CPU.
383 * Platforms that use CPU signatures need to set the signature block to OS and
442 "CPU ECC error loop", /* PTL1_BAD_ECC */
531 CPUSET_DEL(cpuset, CPU->cpu_id);
H A Dcpr_impl.c261 * Since we are coming up from a CPU suspend, the slave cpus
264 for (cp = CPU->cpu_next; cp != CPU; cp = cp->cpu_next) {
269 for (cp = CPU->cpu_next; cp != CPU; cp = cp->cpu_next)
419 cti.index = cpunodes[CPU->cpu_id].dtlb_size - 1;
424 cti.index = cpunodes[CPU->cpu_id].itlb_size - 1;
532 cp = CPU;
538 } while ((cp = cp->cpu_next) != CPU);
1723 cti.index = cpunodes[CPU
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/illumos-gate/usr/src/uts/i86pc/io/pciex/
H A Dnpe_misc.c306 if (!(cpuid_getvendor(CPU) == X86_VENDOR_AMD &&
307 cpuid_getfamily(CPU) >= 0xf))
/illumos-gate/usr/src/uts/common/dtrace/
H A Ddcpc.c44 * DTrace CPU Performance Counter Provider
47 * The DTrace cpc provider allows DTrace consumers to access the CPU
48 * performance counter overflow mechanism of a CPU. The configuration
51 * hardware causes a counter on each CPU to begin counting events of the
60 * subset of the events available for a given CPU. However, when overflow
78 * consumers of the kernel CPU performance counter subsystem (e.g. cpustat(1M)).
150 CPU->cpu_cpcprofile_pc,
151 CPU->cpu_cpcprofile_upc, 0, 0, 0);
168 CPU->cpu_cpcprofile_pc,
169 CPU
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/illumos-gate/usr/src/uts/common/io/
H A Davintr.c110 * the current CPU
115 CPUSET_ATOMIC_DEL(infop->av_pending, CPU->cpu_seqid);
124 return (CPU_IN_SET(infop->av_pending, CPU->cpu_seqid) != 0);
139 * It first sets our av softint pending bit for the current CPU,
140 * then it sets the CPU softint pending bit for pri.
145 CPUSET_ATOMIC_ADD(infop->av_pending, CPU->cpu_seqid);
147 atomic_or_32((uint32_t *)&CPU->cpu_softinfo.st_pending, 1 << pri);
647 * The handler which is executed on the target CPU.
663 int cpuid = CPU->cpu_id;
/illumos-gate/usr/src/uts/sun4u/serengeti/io/
H A Dsbdp_quiesce.c559 if (tp->t_state == TS_ONPROC && tp->t_cpu != CPU)
685 CPU->cpu_id);
759 CPU_SIGNATURE(OS_SIG, SIGST_RUN, SIGSUBST_NULL, CPU->cpu_id);
783 CPU->cpu_id);
853 CPU_SIGNATURE(OS_SIG, SIGST_QUIESCED, SIGSUBST_NULL, CPU->cpu_id);
/illumos-gate/usr/src/uts/sun4/os/
H A Dtrap.c169 CPU_STATS_ADDQ(CPU, sys, trap, 1);
1373 CPU_STATS_ADDQ(CPU, sys, trap, 1);
1596 if (CPU->cpu_runrun || curthread->t_schedflag & TS_ANYWAITQ)
1818 aston(CPU->cpu_dispthread);
1840 * resume: curthread->t_pri == -1 && CPU->dispthread
1841 * != CPU->thread
1848 if (CPU->cpu_dispthread != CPU->cpu_thread)
1856 if (CPU->cpu_dispthread != CPU
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