/illumos-gate/usr/src/uts/common/io/hxge/ |
H A D | hxge_virtual.c | 358 hxge_check_txdma_port_member(p_hxge_t hxgep, uint8_t tdc) argument 370 if (tdc < p_cfgp->max_tdcs)
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H A D | hxge_ndd.c | 1180 int rdc, tdc, block; local 1258 for (tdc = 0; tdc < p_cfgp->max_tdcs; tdc++) { 1260 " %d\t $%p\n", tdc, (void *)tx_rings[tdc]);
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H A D | hxge_txdma.c | 618 uint8_t tdc; local 642 tdc = tx_ring_p->tdc; 655 TXDMA_REG_READ64(handle, TDC_BYTE_CNT, tdc, &byte_cnt.value); 659 "==> hxge_txdma_reclaim: tdc %d tx_rd_index %d " 661 tdc, tx_rd_index, tail_index, tail_wrap, 668 TXDMA_REG_READ64(handle, TDC_TDR_HEAD, tdc, &tx_head.value); 680 TXDMA_REG_READ64(handle, TDC_TDR_QLEN, tdc, &qlen.value); 737 "tdc channel %d opackets %d", 738 pkt_len, tdc, tdc_stat 2410 uint16_t tdc; local 2456 int index, tdc, ndmas; local [all...] |
H A D | hxge_txdma.h | 142 uint16_t tdc; member in struct:_tx_ring_t 182 uint16_t tdc; member in struct:_tx_mbox_t
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H A D | hxge.h | 199 hxge_tx_ring_stats_t tdc_stats[HXGE_MAX_TDCS]; /* per tdc stats */ 316 uint8_t tdc[HXGE_MAX_TDCS]; member in struct:_hxge_t
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/illumos-gate/usr/src/uts/common/io/nxge/npi/ |
H A D | npi_txc.c | 134 * tdc: TX DMA number 143 npi_txc_dump_tdc_fzc_regs(npi_handle_t handle, uint8_t tdc) argument 148 ASSERT(TXDMA_CHANNEL_VALID(tdc)); 149 if (!TXDMA_CHANNEL_VALID(tdc)) { 153 tdc)); 154 return (NPI_FAILURE | NPI_TXC_CHANNEL_INVALID(tdc)); 159 tdc)); 163 offset = TXC_FZC_REG_CN_OFFSET(txc_fzc_dmc_offset[i], tdc); 171 "\n TXC FZC Register Dump for Channel %d done\n", tdc));
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H A D | npi_txdma.c | 117 * Dumps the contents of tdc csrs and fzc registers 120 * tdc: TX DMA number 129 npi_txdma_dump_tdc_regs(npi_handle_t handle, uint8_t tdc) argument 135 ASSERT(TXDMA_CHANNEL_VALID(tdc)); 136 if (!TXDMA_CHANNEL_VALID(tdc)) { 140 tdc)); 142 return (NPI_FAILURE | NPI_TXDMA_CHANNEL_INVALID(tdc)); 147 tdc)); 151 TXDMA_REG_READ64(handle, tdc_dmc_offset[i], tdc, &value); 153 tdc); 208 npi_txdma_tdc_regs_zero(npi_handle_t handle, uint8_t tdc) argument [all...] |
/illumos-gate/usr/src/uts/common/io/nxge/ |
H A D | nxge_ndd.c | 505 0, 0x0fffffff, 0x0fffffff, 0, "dump-tdc", "dump_tdc"}, 996 int tdc; local 1020 for (tdc = 0; tdc < NXGE_MAX_TDCS; tdc++) { 1021 if ((1 << tdc) & set->owned.map) { 1023 buf_len, "%d\n", tdc); 2196 int tdc; local 2200 for (tdc = 0; tdc < NXGE_MAX_TDC 2308 int rdc, tdc, block; local [all...] |
H A D | nxge_txdma.c | 97 int i, tdc, count; local 110 for (tdc = 0; tdc < NXGE_MAX_TDCS; tdc++) { 111 if ((1 << tdc) & map) { 113 group, VP_BOUND_TX, tdc))) 132 for (tdc = 0; tdc < NXGE_MAX_TDCS; tdc++) { 133 if ((1 << tdc) 183 int tdc; local 917 uint8_t tdc; local 1319 int tdc; local 1480 int tdc; local 1568 int tdc; local 1703 int tdc; local 1861 int tdc; local 2014 int tdc; local 2045 int tdc; local 3034 int tdc; local 3087 int tdc; local 3421 nxge_channel_t tdc; local [all...] |
H A D | nxge_virtual.c | 1926 p_cfgp->tdc.start = (func * NXGE_TDMA_PER_NIU_PORT); 1929 p_cfgp->tdc.start = prop_val[0]; 1931 "==> nxge_use_default_dma_config_n2: tdc starts %d " 1932 "(#%d)", p_cfgp->tdc.start, prop_len)); 1936 "==> nxge_use_default_dma_config_n2: #tdc %d (#%d)", 1947 p_cfgp->tdc.count = ndmas; 1948 p_cfgp->tdc.owned = p_cfgp->tdc.count; 1952 p_cfgp, p_cfgp->tdc.count, p_cfgp->tdc 2747 nxge_check_txdma_port_member(p_nxge_t nxgep, uint8_t tdc) argument [all...] |
H A D | nxge_kstats.c | 1224 "kstat_create failed for tdc channel %d", channel)); 2171 int tdc = set[i]; local 2174 val += statsp->tdc_stats[tdc].oerrors; 2178 val += statsp->tdc_stats[tdc].obytes; 2182 val += statsp->tdc_stats[tdc].opackets; 2247 r_index = nxgep->pt_config.hw_config.tdc.start + rhp->index;
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/illumos-gate/usr/src/uts/common/sys/nxge/ |
H A D | nxge_txdma.h | 158 uint16_t tdc; member in struct:_tx_ring_t 205 uint16_t tdc; member in struct:_tx_mbox_t
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H A D | nxge_hio.h | 312 nxge_hio_dc_t tdc[NXGE_MAX_TDCS]; member in struct:__anon8302
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H A D | nxge_common.h | 386 tdc_cfg_t tdc; member in struct:nxge_hw_pt_cfg
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