Searched defs:reg (Results 26 - 50 of 125) sorted by relevance

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/vbox/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/
H A Dfpu_regs.h59 union x86_fpu_reg_u reg; member in struct:x86_fpu_reg
/vbox/src/libs/xpcom18a4/xpcom/obsolete/component/
H A DregExport.cpp51 static void display( nsIRegistry *reg, nsRegistryKey root, const char *name );
52 static void displayValues( nsIRegistry *reg, nsRegistryKey root );
91 nsIRegistry *reg; local
97 (void **) &reg);
112 rv = reg->Open( regFile );
119 display( reg, nsIRegistry::Common, "nsRegistry::Common" );
120 display( reg, nsIRegistry::Users, "nsRegistry::Users" );
122 NS_RELEASE(reg);
131 (void **) &reg);
139 rv = reg
159 display( nsIRegistry *reg, nsRegistryKey root, const char *rootName ) argument
244 displayValues( nsIRegistry *reg, nsRegistryKey root ) argument
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/vbox/src/recompiler/tests/
H A Druncom.c41 static inline uint8_t *seg_to_linear(unsigned int seg, unsigned int reg) argument
43 return (uint8_t *)((seg << 4) + (reg & 0xffff));
H A Dqruncom.c100 static inline uint8_t *seg_to_linear(unsigned int seg, unsigned int reg) argument
102 return (uint8_t *)((seg << 4) + (reg & 0xffff));
/vbox/src/VBox/Devices/PC/ipxe/src/drivers/bus/
H A Dpci.c45 * @v reg PCI register number
55 static unsigned long pci_bar ( struct pci_device *pci, unsigned int reg ) {
59 pci_read_config_dword ( pci, reg, &low );
62 pci_read_config_dword ( pci, reg + 4, &high );
81 * @v reg PCI register number
91 unsigned long pci_bar_start ( struct pci_device *pci, unsigned int reg ) {
94 bar = pci_bar ( pci, reg );
117 int reg; local
119 for ( reg = PCI_BASE_ADDRESS_0; reg <
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/vbox/src/VBox/GuestHost/OpenGL/state_tracker/
H A Dstate_regcombiner.c16 CRRegCombinerState *reg = &ctx->regcombiner; local
20 UNUSED(reg)
25 reg->enabledRegCombiners = GL_FALSE;
27 reg->constantColor0 = zero_color;
29 reg->constantColor1 = zero_color;
34 reg->rgb[i].a = GL_PRIMARY_COLOR_NV;
35 reg->rgb[i].b = GL_ZERO;
36 reg->rgb[i].c = GL_ZERO;
37 reg->rgb[i].d = GL_ZERO;
38 reg
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/vbox/src/VBox/Devices/Bus/
H A DMsiCommon.cpp118 uint32_t reg = i + iOff; local
120 switch (reg)
141 && (reg >= VBOX_MSI_CAP_MASK_BITS_32)
142 && (reg < VBOX_MSI_CAP_MASK_BITS_32 + 4)
145 maskUpdated = reg - VBOX_MSI_CAP_MASK_BITS_32;
148 && (reg >= VBOX_MSI_CAP_MASK_BITS_64)
149 && (reg < VBOX_MSI_CAP_MASK_BITS_64 + 4)
152 maskUpdated = reg - VBOX_MSI_CAP_MASK_BITS_64;
H A DMsixCommon.cpp297 uint32_t reg = i + iOff; local
299 switch (reg)
/vbox/src/VBox/Devices/Graphics/
H A DDevVGA-SVGA3d-shared.h764 static uint32_t vmsvga3dSaveShaderConst(PVMSVGA3DCONTEXT pContext, uint32_t reg, SVGA3dShaderType type, SVGA3dShaderConstType ctype, uint32_t val1, uint32_t val2, uint32_t val3, uint32_t val4) argument
767 AssertReturn(reg < _32K, VERR_INVALID_PARAMETER); argument
771 if (pContext->state.cVertexShaderConst <= reg)
773 pContext->state.paVertexShaderConst = (PVMSVGASHADERCONST)RTMemRealloc(pContext->state.paVertexShaderConst, sizeof(VMSVGASHADERCONST) * (reg + 1));
775 for (uint32_t i = pContext->state.cVertexShaderConst; i < reg + 1; i++)
777 pContext->state.cVertexShaderConst = reg + 1;
780 pContext->state.paVertexShaderConst[reg].fValid = true;
781 pContext->state.paVertexShaderConst[reg].ctype = ctype;
782 pContext->state.paVertexShaderConst[reg].value[0] = val1;
783 pContext->state.paVertexShaderConst[reg]
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/vbox/src/VBox/Devices/PC/ipxe/src/drivers/net/ath/ath5k/
H A Dath5k_reset.c36 #include "reg.h"
173 u32 reg; local
179 reg = AR5K_RATE_DUR(ath5k_bitrate_to_hw_rix(rate));
188 ath5k_hw_reg_write(ah, tx_time, reg);
199 reg + (AR5K_SET_SHORT_PREAMBLE << 2));
/vbox/src/VBox/Devices/PC/ipxe/src/drivers/net/ath/ath9k/
H A Dath9k_init.c438 struct ath_regulatory *reg = ath9k_hw_regulatory(ah); local
447 chan->maxpower = reg->max_power_level / 2;
490 /*struct ath_regulatory *reg;*/
500 /* TODO Cottsay: reg */
507 reg = &common->regulatory;*/
526 /* TODO Cottsay: reg */
528 /*if (!ath_is_world_regd(reg)) {
529 error = regulatory_hint(hw->wiphy, reg->alpha2);
H A Dath9k_mac.c492 u32 reg; local
504 reg = REG_READ(ah, AR_OBS_BUS_1);
507 reg);
/vbox/src/VBox/Devices/PC/ipxe/src/drivers/net/
H A Dnatsemi.c87 uint32_t reg; local
90 reg = readl ( natsemi->regs + NATSEMI_MEAR );
92 return ( reg & mask );
107 uint32_t reg; local
110 reg = readl ( natsemi->regs + NATSEMI_MEAR );
111 reg &= ~mask;
112 reg |= ( data & mask );
113 writel ( reg, natsemi->regs + NATSEMI_MEAR );
448 writel ( ( address & 0xffffffffUL ), natsemi->regs + ring->reg );
452 natsemi->regs + ring->reg
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H A Drealtek.c88 uint8_t reg; local
91 reg = readb ( rtl->regs + RTL_9346CR );
93 return ( reg & mask );
108 uint8_t reg; local
111 reg = readb ( rtl->regs + RTL_9346CR );
112 reg &= ~mask;
113 reg |= ( data & mask );
114 writeb ( reg, rtl->regs + RTL_9346CR );
173 * @v reg Register address
176 static int realtek_mii_read ( struct mii_interface *mii, unsigned int reg ) {
214 realtek_mii_write( struct mii_interface *mii, unsigned int reg, unsigned int data) argument
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H A Dmyson.h67 } __attribute__ (( packed )) reg; member in union:myson_physical_address
150 unsigned int reg; member in struct:myson_ring
158 * @v reg Descriptor base address register
162 unsigned int reg ) {
164 ring->reg = reg;
H A Dpcnet32.c153 pcnet32_mdio_read ( struct net_device *netdev, int phy, int reg )
164 ( ( phy & 0x1f ) << 5 ) | ( reg & 0x1f ) );
173 __unused pcnet32_mdio_write ( struct net_device *netdev, int phy, int reg, int val ) argument
183 ( ( phy & 0x1f ) << 5 ) | ( reg & 0x1f ) );
/vbox/src/VBox/Devices/PC/ipxe/src/drivers/net/rtl818x/
H A Drtl8185_rtl8225.c74 u16 reg = reg80 | !!(bangdata & (1 << i)); local
77 rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, reg);
79 rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, reg | (1 << 1));
80 rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, reg | (1 << 1));
83 rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, reg);
118 u16 reg = reg80 | ((addr >> i) & 1); local
121 rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, reg);
127 reg | (1 << 1));
131 reg | (1 << 1));
136 rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, reg);
282 u32 reg; local
750 u8 reg; local
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H A Drtl818x.c147 u16 reg = rtl818x_ioread16(priv, &priv->map->INT_STATUS); local
149 if (reg == 0xFFFF)
152 rtl818x_iowrite16(priv, &priv->map->INT_STATUS, reg);
154 if (reg & (RTL818X_INT_TXN_OK | RTL818X_INT_TXN_ERR))
157 if (reg & (RTL818X_INT_RX_OK | RTL818X_INT_RX_ERR))
221 u8 reg; local
224 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
226 reg | RTL818X_CONFIG3_ANAPARAM_WRITE);
229 reg & ~RTL818X_CONFIG3_ANAPARAM_WRITE);
236 u16 reg; local
431 u32 reg; local
527 u8 reg; local
606 u8 reg = rtl818x_ioread8(priv, &priv->map->EEPROM_CMD); local
616 u8 reg = rtl818x_ioread8(priv, &priv->map->EEPROM_CMD); local
659 u32 reg; local
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/vbox/src/VBox/ExtPacks/VBoxDTrace/onnv/uts/intel/dtrace/
H A Ddtrace_isa.c548 dtrace_getreg(struct regs *rp, uint_t reg) argument
573 if (reg <= SS) {
574 if (reg >= sizeof (regmap) / sizeof (int)) {
579 reg = regmap[reg];
581 reg -= SS + 1;
584 switch (reg) {
643 if (reg > SS) {
648 return ((&rp->r_gs)[reg]);
/vbox/src/VBox/Additions/WINNT/Graphics/Wine_new/d3d8/
H A Dvertexdeclaration.c117 DWORD reg = ((token & D3DVSD_VERTEXREGMASK) >> D3DVSD_VERTEXREGSHIFT); local
118 TRACE(" 0x%08x REG(%s, %s)\n", token, debug_d3dvsde_register(reg), debug_d3dvsdt_type(type));
126 DWORD reg = ((token & D3DVSD_VERTEXREGMASK) >> D3DVSD_VERTEXREGSHIFT); local
127 TRACE(" 0x%08x TESSUV(%s) as %s\n", token, debug_d3dvsde_register(reg), debug_d3dvsdt_type(type));
294 DWORD reg = ((*token & D3DVSD_VERTEXREGMASK) >> D3DVSD_VERTEXREGSHIFT); local
302 element->output_slot = reg;
304 element->usage = wined3d_usage_lookup[reg].usage;
305 element->usage_idx = wined3d_usage_lookup[reg].usage_idx;
/vbox/src/VBox/Additions/WINNT/Graphics/Wine/d3d8/
H A Dvertexdeclaration.c175 DWORD reg = ((token & D3DVSD_VERTEXREGMASK) >> D3DVSD_VERTEXREGSHIFT); local
176 TRACE(" 0x%08x REG(%s, %s)\n", token, debug_d3dvsde_register(reg), debug_d3dvsdt_type(type));
184 DWORD reg = ((token & D3DVSD_VERTEXREGMASK) >> D3DVSD_VERTEXREGSHIFT); local
185 TRACE(" 0x%08x TESSUV(%s) as %s\n", token, debug_d3dvsde_register(reg), debug_d3dvsdt_type(type));
350 DWORD reg = ((*token & D3DVSD_VERTEXREGMASK) >> D3DVSD_VERTEXREGSHIFT); local
358 element->output_slot = reg;
360 element->usage = wined3d_usage_lookup[reg].usage;
361 element->usage_idx = wined3d_usage_lookup[reg].usage_idx;
/vbox/src/VBox/Devices/PC/ipxe/src/core/
H A Di82365.c120 static u_char i365_get(u_short sock, u_short reg) argument
127 reg = I365_REG(pccsock[sock].internalid, reg);
128 outb(reg, port); val = inb(port+1);
134 static void i365_set(u_short sock, u_short reg, u_char data) argument
140 u_char val = I365_REG(pccsock[sock].internalid, reg);
164 void i365_bset(u_short sock, u_short reg, u_char mask) { argument
165 u_char d = i365_get(sock, reg);
167 i365_set(sock, reg, d);
170 void i365_bclr(u_short sock, u_short reg, u_cha argument
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/vbox/src/VBox/Devices/PC/ipxe/src/drivers/net/igbvf/
H A Digbvf.h364 static inline u32 __er32(struct e1000_hw *hw, unsigned long reg) argument
366 return readl(hw->hw_addr + reg);
369 static inline void __ew32(struct e1000_hw *hw, unsigned long reg, u32 val) argument
371 writel(val, hw->hw_addr + reg);
373 #define er32(reg) E1000_READ_REG(hw, E1000_##reg)
374 #define ew32(reg,val) E1000_WRITE_REG(hw, E1000_##reg, (val))
/vbox/src/VBox/Additions/x11/x11include/xorg-server-1.16.0/
H A Dregionstr.h72 RegionNil(RegionPtr reg) argument
74 return ((reg)->data && !(reg)->data->numRects);
80 RegionNar(RegionPtr reg) argument
82 return ((reg)->data == &RegionBrokenData);
86 RegionNumRects(RegionPtr reg) argument
88 return ((reg)->data ? (reg)->data->numRects : 1);
92 RegionSize(RegionPtr reg) argument
94 return ((reg)
98 RegionRects(RegionPtr reg) argument
104 RegionBoxptr(RegionPtr reg) argument
110 RegionBox(RegionPtr reg, int i) argument
116 RegionTop(RegionPtr reg) argument
122 RegionEnd(RegionPtr reg) argument
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/vbox/src/VBox/Additions/x11/x11include/xorg-server-1.17.1/
H A Dregionstr.h72 RegionNil(RegionPtr reg) argument
74 return ((reg)->data && !(reg)->data->numRects);
80 RegionNar(RegionPtr reg) argument
82 return ((reg)->data == &RegionBrokenData);
86 RegionNumRects(RegionPtr reg) argument
88 return ((reg)->data ? (reg)->data->numRects : 1);
92 RegionSize(RegionPtr reg) argument
94 return ((reg)
98 RegionRects(RegionPtr reg) argument
104 RegionBoxptr(RegionPtr reg) argument
110 RegionBox(RegionPtr reg, int i) argument
116 RegionTop(RegionPtr reg) argument
122 RegionEnd(RegionPtr reg) argument
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