Searched defs:mxcsr (Results 1 - 16 of 16) sorted by relevance

/illumos-gate/usr/src/lib/libc/amd64/fp/
H A Dfpgetsticky.c38 int sw, mxcsr; local
41 _getmxcsr(&mxcsr);
42 sw |= mxcsr;
H A Dfpsetsticky.c38 int sw, mxcsr; local
42 _getmxcsr(&mxcsr);
43 sw |= mxcsr;
44 mxcsr = (mxcsr & ~0x3f) | ((int)s & 0x3f);
45 _putmxcsr(mxcsr);
H A Dfpsetmask.c46 int mxcsr; local
52 _getmxcsr(&mxcsr);
53 mxcsr = (mxcsr & ~0x1f80) | (~((int)newmask << 7) & 0x1f80);
54 _putmxcsr(mxcsr);
H A Dfpsetround.c46 int mxcsr; local
53 _getmxcsr(&mxcsr);
54 mxcsr = (mxcsr & ~0x6000) | ((int)newrnd << 13);
55 _putmxcsr(mxcsr);
/illumos-gate/usr/src/lib/libc/i386/fp/
H A Dfpgetsticky.c40 int sw, mxcsr; local
44 _getmxcsr(&mxcsr);
45 sw |= mxcsr;
H A Dfpsetsticky.c40 int sw, mxcsr; local
45 _getmxcsr(&mxcsr);
46 sw |= mxcsr;
47 mxcsr = (mxcsr & ~0x3f) | ((int)s & 0x3f);
48 _putmxcsr(mxcsr);
H A Dfpsetmask.c47 int mxcsr; local
54 _getmxcsr(&mxcsr);
55 mxcsr = (mxcsr & ~0x1f80) | (~((int)newmask << 7) & 0x1f80);
56 _putmxcsr(mxcsr);
H A Dfpsetround.c47 int mxcsr; local
66 _getmxcsr(&mxcsr);
67 mxcsr = (mxcsr & ~0x6000) | ((int)newrnd << 13);
68 _putmxcsr(mxcsr);
/illumos-gate/usr/src/lib/libm/common/m9x/
H A D__fex_sse.c471 * of trapped exception (if any). On entry, the mxcsr must have
481 unsigned int e, te, mxcsr, oldmxcsr, subnorm; local
803 __fenv_getmxcsr(&mxcsr);
804 info->flags = mxcsr & 0x3d;
808 te = ~(uap->uc_mcontext.fpregs.fp_reg_set.fpchip_state.mxcsr
810 e = mxcsr & te;
H A D__fex_i386.c93 unsigned int cwsw, mxcsr; local
100 flag) from mxcsr */
101 __fenv_getmxcsr(&mxcsr);
102 cwsw |= (mxcsr & 0x3d);
111 unsigned int cwsw, mxcsr; local
121 (excluding denormal operand mask and flag) to mxcsr */
122 __fenv_getmxcsr(&mxcsr);
123 mxcsr = (mxcsr & ~0x7ebd) | ((cwsw >> 13) & 0x6000) |
125 __fenv_setmxcsr(&mxcsr);
[all...]
H A D__fex_hdlr.c394 unsigned int cwsw, oldcwsw, mxcsr, oldmxcsr; local
412 mxcsr = (oldmxcsr & ~0x3f) | 0x1f80;
413 __fenv_setmxcsr(&mxcsr);
421 fpchip_state.mxcsr;
499 __fenv_setmxcsr(&mxcsr);
544 fpchip_state.mxcsr & ~te_bit[(int)e];
574 __fenv_setmxcsr(&mxcsr);
644 mxcsr;
665 __fenv_getmxcsr(&mxcsr);
666 mxcsr
[all...]
/illumos-gate/usr/src/uts/intel/ia32/os/
H A Dfpu.c596 uint32_t mxcsr, xmask; local
623 mxcsr = fp->fpu_regs.kfpu_u.kfpu_fx.fx_mxcsr;
627 fp->fpu_regs.kfpu_xstatus = mxcsr;
634 xmask = (mxcsr >> 7) & SSE_MXCSR_EFLAGS;
635 return (fpe_simd_sicode((mxcsr & SSE_MXCSR_EFLAGS) & ~xmask));
697 fpsetcw(uint16_t fcw, uint32_t mxcsr) argument
706 if (fcw == FPU_CW_INIT && mxcsr == SSE_MXCSR_INIT) {
740 fx->fx_mxcsr = sse_mxcsr_mask & mxcsr;
746 fx->fx_mxcsr = sse_mxcsr_mask & mxcsr;
/illumos-gate/usr/src/cmd/mdb/intel/mdb/
H A Dproc_ia32dep.c329 fpmxcsr2str(uint32_t mxcsr, char *buf, size_t nbytes) argument
339 if (mxcsr & SSE_IE)
341 if (mxcsr & SSE_DE)
343 if (mxcsr & SSE_ZE)
345 if (mxcsr & SSE_OE)
347 if (mxcsr & SSE_UE)
349 if (mxcsr & SSE_PE)
352 if (mxcsr & SSE_DAZ)
355 if (mxcsr & SSE_IM)
357 if (mxcsr
[all...]
H A Dproc_amd64dep.c388 fpmxcsr2str(uint32_t mxcsr, char *buf, size_t nbytes) argument
398 if (mxcsr & SSE_IE)
400 if (mxcsr & SSE_DE)
402 if (mxcsr & SSE_ZE)
404 if (mxcsr & SSE_OE)
406 if (mxcsr & SSE_UE)
408 if (mxcsr & SSE_PE)
411 if (mxcsr & SSE_DAZ)
414 if (mxcsr & SSE_IM)
416 if (mxcsr
[all...]
/illumos-gate/usr/src/uts/intel/sys/
H A Dmcontext.h103 uint32_t mxcsr; member in struct:_fpu::__anon505::_fpchip_state
112 uint32_t xstatus; /* mxcsr at exception */
132 uint32_t mxcsr; /* SSE control and status */ member in struct:_fpu::__anon507::_fpchip_state
133 uint32_t xstatus; /* SSE mxcsr at exception */
156 uint32_t mxcsr; /* SSE control and status */ member in struct:fpu32::__anon508::fpchip32_state
157 uint32_t xstatus; /* SSE mxcsr at exception */
/illumos-gate/usr/src/head/
H A Dieeefp.h248 unsigned int mxcsr; member in struct:_fpstate
261 * The structure of the 80*87 status and control words, and the mxcsr

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