Searched defs:msg_valid_state (Results 1 - 3 of 3) sorted by relevance
/illumos-gate/usr/src/uts/sun4v/io/px/ |
H A D | px_lib4v.c | 1180 pcie_msg_valid_state_t *msg_valid_state) 1188 msg_valid_state)) != H_EOK) { 1194 DBG(DBG_LIB_MSI, dip, "px_lib_msg_getvalid: msg_valid_state 0x%x\n", 1195 *msg_valid_state); 1203 pcie_msg_valid_state_t msg_valid_state) 1208 "msg_valid_state 0x%x\n", dip, msg_type, msg_valid_state); 1211 msg_valid_state)) != H_EOK) { 1179 px_lib_msg_getvalid(dev_info_t *dip, pcie_msg_type_t msg_type, pcie_msg_valid_state_t *msg_valid_state) argument 1202 px_lib_msg_setvalid(dev_info_t *dip, pcie_msg_type_t msg_type, pcie_msg_valid_state_t msg_valid_state) argument
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/illumos-gate/usr/src/uts/sun4u/io/px/ |
H A D | px_hlib.c | 2574 pcie_msg_valid_state_t *msg_valid_state) 2580 *msg_valid_state = CSR_BR((caddr_t)dev_hdl, PM_PME_MAPPING, V); 2583 *msg_valid_state = CSR_BR((caddr_t)dev_hdl, 2587 *msg_valid_state = CSR_BR((caddr_t)dev_hdl, ERR_COR_MAPPING, V); 2590 *msg_valid_state = CSR_BR((caddr_t)dev_hdl, 2594 *msg_valid_state = CSR_BR((caddr_t)dev_hdl, ERR_FATAL_MAPPING, 2607 pcie_msg_valid_state_t msg_valid_state) 2611 switch (msg_valid_state) { 2573 hvio_msg_getvalid(devhandle_t dev_hdl, pcie_msg_type_t msg_type, pcie_msg_valid_state_t *msg_valid_state) argument 2606 hvio_msg_setvalid(devhandle_t dev_hdl, pcie_msg_type_t msg_type, pcie_msg_valid_state_t msg_valid_state) argument
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H A D | px_lib4u.c | 1271 pcie_msg_valid_state_t *msg_valid_state) 1279 msg_valid_state)) != H_EOK) { 1285 DBG(DBG_LIB_MSI, dip, "px_lib_msg_getvalid: msg_valid_state 0x%x\n", 1286 *msg_valid_state); 1294 pcie_msg_valid_state_t msg_valid_state) 1299 "msg_valid_state 0x%x\n", dip, msg_type, msg_valid_state); 1302 msg_valid_state)) != H_EOK) { 1270 px_lib_msg_getvalid(dev_info_t *dip, pcie_msg_type_t msg_type, pcie_msg_valid_state_t *msg_valid_state) argument 1293 px_lib_msg_setvalid(dev_info_t *dip, pcie_msg_type_t msg_type, pcie_msg_valid_state_t msg_valid_state) argument
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