Searched defs:iommu (Results 1 - 6 of 6) sorted by relevance

/illumos-gate/usr/src/uts/i86pc/io/amd_iommu/
H A Damd_iommu_cmd.c34 amd_iommu_wait_for_completion(amd_iommu_t *iommu) argument
36 ASSERT(MUTEX_HELD(&iommu->aiomt_cmdlock));
38 iommu->aiomt_reg_status_va), AMD_IOMMU_COMWAIT_INT) != 1) {
39 AMD_IOMMU_REG_SET64(REGADDR64(iommu->aiomt_reg_ctrl_va),
46 create_compl_wait_cmd(amd_iommu_t *iommu, amd_iommu_cmdargs_t *cmdargsp, argument
49 const char *driver = ddi_driver_name(iommu->aiomt_dip);
50 int instance = ddi_get_instance(iommu->aiomt_dip);
58 f, driver, instance, iommu->aiomt_idx);
78 create_inval_devtab_entry_cmd(amd_iommu_t *iommu, amd_iommu_cmdargs_t *cmdargsp, argument
81 const char *driver = ddi_driver_name(iommu
108 create_inval_iommu_pages_cmd(amd_iommu_t *iommu, amd_iommu_cmdargs_t *cmdargsp, amd_iommu_cmd_flags_t flags, uint32_t *cmdptr) argument
139 create_inval_iotlb_pages_cmd(amd_iommu_t *iommu, amd_iommu_cmdargs_t *cmdargsp, amd_iommu_cmd_flags_t flags, uint32_t *cmdptr) argument
170 create_inval_intr_table_cmd(amd_iommu_t *iommu, amd_iommu_cmdargs_t *cmdargsp, amd_iommu_cmd_flags_t flags, uint32_t *cmdptr) argument
196 amd_iommu_cmd(amd_iommu_t *iommu, amd_iommu_cmd_t cmd, amd_iommu_cmdargs_t *cmdargs, amd_iommu_cmd_flags_t flags, int lock_held) argument
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H A Damd_iommu_log.c116 devtab_illegal_entry(amd_iommu_t *iommu, uint32_t *event) argument
125 const char *driver = ddi_driver_name(iommu->aiomt_dip);
126 int instance = ddi_get_instance(iommu->aiomt_dip);
155 f, driver, instance, iommu->aiomt_idx,
165 io_page_fault(amd_iommu_t *iommu, uint32_t *event) argument
177 const char *driver = ddi_driver_name(iommu->aiomt_dip);
178 int instance = ddi_get_instance(iommu->aiomt_dip);
209 f, driver, instance, iommu->aiomt_idx,
223 devtab_hw_error(amd_iommu_t *iommu, uint32_t *event) argument
233 const char *driver = ddi_driver_name(iommu
272 pgtable_hw_error(amd_iommu_t *iommu, uint32_t *event) argument
325 cmdbuf_illegal_cmd(amd_iommu_t *iommu, uint32_t *event) argument
348 cmdbuf_hw_error(amd_iommu_t *iommu, uint32_t *event) argument
379 iotlb_inval_to(amd_iommu_t *iommu, uint32_t *event) argument
418 device_illegal_req(amd_iommu_t *iommu, uint32_t *event) argument
458 amd_iommu_process_one_event(amd_iommu_t *iommu) argument
509 amd_iommu_read_log(amd_iommu_t *iommu, amd_iommu_log_op_t op) argument
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H A Damd_iommu_acpi.c796 set_deventry(amd_iommu_t *iommu, int entry, amd_iommu_acpi_ivhd_t *hinfop) argument
801 &iommu->aiomt_devtbl[entry * AMD_IOMMU_DEVTBL_ENTRY_SZ];
809 amd_iommu_acpi_init_devtbl(amd_iommu_t *iommu) argument
818 if (hinfop->ach_IOMMU_deviceid != iommu->aiomt_bdf)
824 set_deventry(iommu, j, hinfop);
828 set_deventry(iommu,
837 set_deventry(iommu, j, hinfop);
842 set_deventry(iommu,
899 amd_iommu_lookup_any_ivhd(amd_iommu_t *iommu) argument
907 hinfop->ach_IOMMU_deviceid == iommu
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H A Damd_iommu_impl.c39 static int amd_iommu_fini(amd_iommu_t *iommu, int type);
40 static void amd_iommu_teardown_interrupts(amd_iommu_t *iommu);
41 static void amd_iommu_stop(amd_iommu_t *iommu);
68 static int unmap_current_window(amd_iommu_t *iommu, dev_info_t *rdip,
114 amd_iommu_register(amd_iommu_t *iommu) argument
116 dev_info_t *dip = iommu->aiomt_dip;
127 iommulib_ops->ilops_data = (void *)iommu;
128 iommu->aiomt_iommulib_ops = iommulib_ops;
133 "failed idx=%d", f, driver, instance, iommu->aiomt_idx);
138 iommu
144 amd_iommu_unregister(amd_iommu_t *iommu) argument
164 amd_iommu_setup_passthru(amd_iommu_t *iommu) argument
187 amd_iommu_start(amd_iommu_t *iommu) argument
246 amd_iommu_stop(amd_iommu_t *iommu) argument
276 amd_iommu_setup_tables_and_buffers(amd_iommu_t *iommu) argument
483 amd_iommu_teardown_tables_and_buffers(amd_iommu_t *iommu, int type) argument
544 amd_iommu_enable_interrupts(amd_iommu_t *iommu) argument
565 amd_iommu_setup_exclusion(amd_iommu_t *iommu) argument
601 amd_iommu_teardown_exclusion(amd_iommu_t *iommu) argument
610 amd_iommu_t *iommu = (amd_iommu_t *)arg1; local
656 amd_iommu_setup_interrupts(amd_iommu_t *iommu) argument
882 amd_iommu_teardown_interrupts(amd_iommu_t *iommu) argument
923 amd_iommu_t *iommu; local
1184 amd_iommu_fini(amd_iommu_t *iommu, int type) argument
1249 amd_iommu_t *iommu; local
1347 amd_iommu_t *iommu, *next_iommu; local
1419 amd_iommu_t *iommu = iommulib_iommu_getdata(handle); local
1494 map_current_window(amd_iommu_t *iommu, dev_info_t *rdip, ddi_dma_attr_t *attrp, struct ddi_dma_req *dmareq, ddi_dma_cookie_t *cookie_array, uint_t ccount, int km_flags) argument
1554 unmap_current_window(amd_iommu_t *iommu, dev_info_t *rdip, ddi_dma_cookie_t *cookie_array, uint_t ccount, int ncookies, int locked) argument
1628 amd_iommu_t *iommu = iommulib_iommu_getdata(handle); local
1707 amd_iommu_t *iommu = iommulib_iommu_getdata(handle); local
1810 amd_iommu_t *iommu = iommulib_iommu_getdata(handle); local
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H A Damd_iommu_page_tables.c64 amd_iommu_get_src_bdf(amd_iommu_t *iommu, int32_t bdf, int32_t *src_bdfp) argument
87 amd_iommu_get_domain(amd_iommu_t *iommu, dev_info_t *rdip, int alias, argument
124 amd_iommu_init_page_tables(amd_iommu_t *iommu) argument
132 amd_iommu_fini_page_tables(amd_iommu_t *iommu) argument
142 amd_iommu_lookup_domain(amd_iommu_t *iommu, domain_id_t domainid, argument
170 iommu->aiomt_idx, domainid);
196 amd_iommu_teardown_domain(amd_iommu_t *iommu, amd_iommu_domain_t *dp) argument
228 if (amd_iommu_cmd(iommu, AMD_IOMMU_CMD_INVAL_IOMMU_PAGES,
232 f, iommu->aiomt_idx, cmdargs.ca_domainid);
237 amd_iommu_get_deviceid(amd_iommu_t *iommu, dev_info_ argument
328 init_devtbl(amd_iommu_t *iommu, uint64_t *devtbl_entry, domain_id_t domainid, amd_iommu_domain_t *dp) argument
387 amd_iommu_set_passthru(amd_iommu_t *iommu, dev_info_t *rdip) argument
479 amd_iommu_set_devtbl_entry(amd_iommu_t *iommu, dev_info_t *rdip, domain_id_t domainid, uint16_t deviceid, amd_iommu_domain_t *dp, const char *path) argument
554 amd_iommu_clear_devtbl_entry(amd_iommu_t *iommu, dev_info_t *rdip, domain_id_t domainid, uint16_t deviceid, amd_iommu_domain_t *dp, int *domain_freed, char *path) argument
712 amd_iommu_lookup_pgtable(amd_iommu_t *iommu, amd_iommu_page_table_t *ppt, amd_iommu_domain_t *dp, int level, uint16_t index) argument
769 amd_iommu_alloc_pgtable(amd_iommu_t *iommu, domain_id_t domainid, const char *path, amd_iommu_page_table_t **ptp, int km_flags) argument
923 amd_iommu_free_pgtable(amd_iommu_t *iommu, amd_iommu_page_table_t *pt) argument
1091 amd_iommu_setup_1_pgtable(amd_iommu_t *iommu, dev_info_t *rdip, struct ddi_dma_req *dmareq, domain_id_t domainid, amd_iommu_domain_t *dp, amd_iommu_page_table_t *ppt, uint16_t index, int level, uint64_t va, uint64_t pa, amd_iommu_page_table_t **ptp, uint16_t *next_idxp, const char *path, int km_flags) argument
1162 amd_iommu_teardown_pdte(amd_iommu_t *iommu, amd_iommu_page_table_t *pt, int index) argument
1209 amd_iommu_create_pgtables(amd_iommu_t *iommu, dev_info_t *rdip, struct ddi_dma_req *dmareq, uint64_t va, uint64_t pa, uint16_t deviceid, domain_id_t domainid, amd_iommu_domain_t *dp, const char *path, int km_flags) argument
1285 amd_iommu_destroy_pgtables(amd_iommu_t *iommu, dev_info_t *rdip, uint64_t pageva, uint16_t deviceid, domain_id_t domainid, amd_iommu_domain_t *dp, map_type_t type, int *domain_freed, char *path) argument
1434 amd_iommu_map_pa2va(amd_iommu_t *iommu, dev_info_t *rdip, ddi_dma_attr_t *attrp, struct ddi_dma_req *dmareq, uint64_t start_pa, uint64_t pa_sz, map_type_t type, uint64_t *start_vap, int km_flags) argument
1595 amd_iommu_unmap_va(amd_iommu_t *iommu, dev_info_t *rdip, uint64_t start_va, uint64_t va_sz, map_type_t type) argument
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/illumos-gate/usr/src/uts/sun4u/sys/pci/
H A Dpci_iommu.h50 * The following macros define the iommu page size and related operations.
79 * and iommu bypass transfers.
89 * For iommu bypass addresses, bit 43 specifies cacheability.
94 * Generic iommu definitions and types:
119 * iommu block soft state structure:
121 * Each pci node may share an iommu block structure with its peer
122 * node of have its own private iommu block structure.
124 typedef struct iommu iommu_t;
125 struct iommu { struct
137 * virtual and physical addresses and size of the iommu ts
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