Searched defs:MISC_REG_AEU_ENABLE4_FUNC_0_OUT_3 (Results 1 - 1 of 1) sorted by relevance

/illumos-gate/usr/src/uts/common/io/bnxe/577xx/hsi/hw/include/
H A D57712_reg.h5405 #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_3 0xa0a8UL //ACCESS:RW DataWidth:0x20 Description: fourth 32b for enabling the output for function 0 output3.mapped as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3] General attn5; [4] General attn6; [5] General attn7; [6] General attn8; [7] General attn9; [8] General attn10; [9] General attn11; [10] General attn12; [11] General attn13; [12] General attn14; [13] General attn15; [14] General attn16; [15] General attn17; [16] General attn18; [17] General attn19; [18] General attn20; [19] General attn21; [20] Main power interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC Latched timeout attention; [27] GRC Latched reserved access attention; [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP Latched ump_tx_parity; [31] MCP Latched scpad_parity; macro
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