Searched defs:MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0 (Results 1 - 1 of 1) sorted by relevance

/illumos-gate/usr/src/uts/common/io/bnxe/577xx/hsi/hw/include/
H A D57712_reg.h5390 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0 0xa06cUL //ACCESS:RW DataWidth:0x20 Description: first 32b for enabling the output for function 0 output0. mapped as follows: [0] NIG attention for function0; [1] NIG attention for function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] TSEMI Hw interrupt; [30] PBClient Parity error; [31] PBClient Hw interrupt; macro
[all...]

Completed in 477 milliseconds