/vbox/src/VBox/Devices/EFI/Firmware/IntelFrameworkPkg/Include/Protocol/ |
H A D | SmmCpuIo.h | 83 EFI_SMM_IO_ACCESS Io; member in struct:_EFI_SMM_CPU_IO_INTERFACE
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/vbox/src/VBox/Devices/EFI/Firmware/MdePkg/Include/Protocol/ |
H A D | SmmCpuIo2.h | 91 EFI_SMM_IO_ACCESS2 Io; member in struct:_EFI_SMM_CPU_IO2_PROTOCOL
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H A D | CpuIo2.h | 62 The Io.Read() and Io.Write() functions enable a driver to access PCI controller 137 EFI_CPU_IO_PROTOCOL_ACCESS Io; member in struct:_EFI_CPU_IO2_PROTOCOL
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H A D | DeviceIo.h | 253 EFI_IO_ACCESS Io; member in struct:_EFI_DEVICE_IO_PROTOCOL
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H A D | PciRootBridgeIo.h | 431 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_ACCESS Io; member in struct:_EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
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H A D | PciIo.h | 527 EFI_PCI_IO_PROTOCOL_ACCESS Io; member in struct:_EFI_PCI_IO_PROTOCOL
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/vbox/src/VBox/Devices/PC/ipxe/src/include/ipxe/efi/Protocol/ |
H A D | CpuIo2.h | 64 The Io.Read() and Io.Write() functions enable a driver to access PCI controller 139 EFI_CPU_IO_PROTOCOL_ACCESS Io; member in struct:_EFI_CPU_IO2_PROTOCOL
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H A D | PciRootBridgeIo.h | 418 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_ACCESS Io; member in struct:_EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
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H A D | PciIo.h | 529 EFI_PCI_IO_PROTOCOL_ACCESS Io; member in struct:_EFI_PCI_IO_PROTOCOL
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/vbox/src/VBox/Devices/EFI/Firmware/IntelFrameworkModulePkg/Include/Protocol/ |
H A D | IsaIo.h | 336 EFI_ISA_IO_PROTOCOL_ACCESS Io; member in struct:_EFI_ISA_IO_PROTOCOL
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/vbox/src/VBox/Devices/EFI/Firmware/MdePkg/Include/Ppi/ |
H A D | CpuIo.h | 403 EFI_PEI_CPU_IO_PPI_ACCESS Io; member in struct:_EFI_PEI_CPU_IO_PPI
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/vbox/src/VBox/Devices/EFI/Firmware/IntelFrameworkModulePkg/Bus/Isa/IsaIoDxe/ |
H A D | IsaIo.c | 294 EFI_ACPI_IO_PORT_DESCRIPTOR *Io; local 329 Io = (EFI_ACPI_IO_PORT_DESCRIPTOR *) AcpiResource.SmallHeader; 330 if (Io->Length != 0) { 333 IsaResource[Count].Attribute = IsaIoAttribute (Io->Information); 334 IsaResource[Count].StartRange = Io->BaseAddressMin; 335 IsaResource[Count].EndRange = Io->BaseAddressMin + Io->Length - 1; 552 Status = IsaIoDevice->PciIo->Io.Read ( 614 Status = IsaIoDevice->PciIo->Io.Write ( 657 Status = IsaIoDevice->PciIo->Io [all...] |
/vbox/src/VBox/Devices/EFI/Firmware/PcAtChipsetPkg/PciHostBridgeDxe/ |
H A D | PciHostBridge.h | 463 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL Io; member in struct:__anon12666 472 CR(a, PCI_ROOT_BRIDGE_INSTANCE, Io, PCI_ROOT_BRIDGE_SIGNATURE) 480 Construct the Pci Root Bridge Io protocol
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/vbox/src/VBox/Devices/Storage/VSCSI/ |
H A D | VSCSIInternal.h | 150 } Io; member in union:VSCSIIOREQINT::__anon15957
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/vbox/src/VBox/Storage/Debug/ |
H A D | VDDbgIoLog.cpp | 83 } Io; member in union:IoLogEntryStart::__anon16775 403 Entry.Io.u64Off = RT_H2LE_U64(off); 404 Entry.Io.u64IoSize = RT_H2LE_U64(cbIo); 670 *poff = RT_LE2H_U64(Entry.Io.u64Off); 671 *pcbIo = RT_LE2H_U64(Entry.Io.u64IoSize);
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/vbox/src/VBox/Storage/ |
H A D | VD.cpp | 397 } Io; member in union:VDIOCTX::__anon16785 1010 RTSgBufReset(&pIoCtx->Req.Io.SgBuf); 1033 RTSgBufReset(&pIoCtx->Req.Io.SgBuf); 1042 RTSgBufReset(&pIoCtx->Req.Io.SgBuf); 1052 pIoCtx->rcReq = vdFilterChainApplyRead(pDisk, pIoCtx->Req.Io.uOffsetXferOrig, 1053 pIoCtx->Req.Io.cbXferOrig, pIoCtx); 1070 pIoCtx->Req.Io.cbTransferLeft = (uint32_t)cbTransfer; Assert((uint32_t)cbTransfer == cbTransfer); 1071 pIoCtx->Req.Io.uOffset = uOffset; 1072 pIoCtx->Req.Io.cbTransfer = cbTransfer; 1073 pIoCtx->Req.Io [all...] |
/vbox/src/VBox/Devices/Storage/ |
H A D | DevAHCI.cpp | 345 } Io; member in union:AHCIREQ::__anon15815 4350 uint8_t *pbBufSrc = (uint8_t *)pAhciReq->u.Io.DataSeg.pvSeg; 4396 pAhciReq->u.Io.pfnPostProcess = atapiReadSectors2352PostProcess; 5613 pAhciReq->u.Io.DataSeg.pvSeg = ahciReqMemAlloc(pAhciPort, pAhciReq, cbTransfer); 5614 if (!pAhciReq->u.Io.DataSeg.pvSeg) 5617 pAhciReq->u.Io.DataSeg.cbSeg = cbTransfer; 5621 pAhciReq->u.Io.DataSeg.pvSeg, 5646 if (pAhciReq->u.Io.pfnPostProcess) 5650 int rc = pAhciReq->u.Io.pfnPostProcess(pAhciReq, &pv, &cb); 5660 pAhciReq->u.Io [all...] |