Searched defs:IGU_REG_TRAILING_EDGE_LATCH (Results 1 - 1 of 1) sorted by relevance

/illumos-gate/usr/src/uts/common/io/bnxe/577xx/hsi/hw/include/
H A D57712_reg.h5272 #define IGU_REG_TRAILING_EDGE_LATCH 0x130104UL //ACCESS:RW DataWidth:0x10 SPLIT:8 Description: Attention signals trailing edge. attn bit condition monitoring; each bit that is set will lock a change from 1 to 0 in the corresponding attention signals that comes from the AEU macro
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