Searched defs:IGU_REG_PENDING_BITS_STATUS (Results 1 - 1 of 1) sorted by relevance

/illumos-gate/usr/src/uts/common/io/bnxe/577xx/hsi/hw/include/
H A D57712_reg.h5336 #define IGU_REG_PENDING_BITS_STATUS 0x130300UL //ACCESS:WB_R DataWidth:0x20 Description: Each bit represent the pending bits status for that SB. 0 = no pending; 1 = pending. Pendings means interrupt was asserted; and write done was not received. Data valid only in addresses 0-4. all the rest are zero. macro
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