Searched defs:CPU (Results 1 - 6 of 6) sorted by relevance

/illumos-gate/usr/src/lib/libdtrace_jni/java/src/org/opensolaris/os/dtrace/
H A DInterfaceAttributes.java231 * The interface is specific to the CPU model of the current
233 * -v} option to display the current CPU model and
234 * implementation names. Interfaces with CPU model dependencies
235 * might not be available on other CPU implementations, even if
237 * (ISA). For example, a CPU-dependent interface on an
242 CPU("CPU"), enum constant in enum:InterfaceAttributes.DependencyClass
246 * and architectural characteristics such as a set of supported CPU
H A DProbeData.java83 new String[] {"enabledProbeID", "CPU",
125 CPU, enum constant in enum:ProbeData.KeyField
158 * @param cpuID non-negative ID, identifies the CPU on which the
628 case CPU:
676 * Gets the ID of the CPU on which the probe fired.
678 * @return ID of the CPU on which the probe fired
/illumos-gate/usr/src/cmd/pools/common/
H A Dutils.h89 #define CPU "cpu" macro
/illumos-gate/usr/src/lib/fm/topo/libtopo/common/
H A Dtopo_hc.h49 #define CPU "cpu" macro
/illumos-gate/usr/src/uts/common/sys/
H A Dcpuvar.h75 * Per-CPU data.
83 processorid_t cpu_id; /* CPU number */
84 processorid_t cpu_seqid; /* sequential CPU id (0..ncpus-1) */
85 volatile cpu_flag_t cpu_flags; /* flags indicating CPU state */
88 kthread_t *cpu_idle_thread; /* idle thread for this CPU */
89 kthread_t *cpu_pause_thread; /* pause thread for this CPU */
92 struct cpupart *cpu_part; /* partition with this CPU */
105 struct cpu *cpu_next; /* next existing CPU */
106 struct cpu *cpu_prev; /* prev existing CPU */
107 struct cpu *cpu_next_onln; /* next online (enabled) CPU */
567 #define CPU macro
569 #define CPU macro
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/illumos-gate/usr/src/lib/libumem/common/
H A Dumem.c55 * * CPU handling
148 * 3. CPU handling
150 * kmem uses the CPU's sequence number to determine which "cpu cache" to
157 * The mechanics of this is all in the CPU(mask) macro.
382 * Time may be an illusion, but CPU cycles aren't. While libumem is designed
385 * a per-CPU lock for each allocation. When contention is low and malloc(3C)
692 uint32_t umem_max_ncpus; /* # of CPU caches. */
703 size_t umem_failure_log_size; /* failure log [4 pages per CPU] */
704 size_t umem_slab_log_size; /* slab create log [4 pages per CPU] */
757 #define CPU(mas macro
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