26  * DEF(name, oargs, iargs, cargs, flags)
30 DEF(end, 0, 0, 0, 0) /* must be kept first */
31 DEF(nop, 0, 0, 0, 0)
32 DEF(nop1, 0, 0, 1, 0)
33 DEF(nop2, 0, 0, 2, 0)
34 DEF(nop3, 0, 0, 3, 0)
35 DEF(nopn, 0, 0, 1, 0) /* variable number of parameters */
37 DEF(discard, 1, 0, 0, 0)
39 DEF(set_label, 0, 0, 1, 0)
40 DEF(call, 0, 1, 2, TCG_OPF_SIDE_EFFECTS) /* variable number of parameters */
41 DEF(jmp, 0, 1, 0, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
42 DEF(br, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
44 DEF(mov_i32, 1, 1, 0, 0)
45 DEF(movi_i32, 1, 0, 1, 0)
46 DEF(setcond_i32, 1, 2, 1, 0)
48 DEF(ld8u_i32, 1, 1, 1, 0)
49 DEF(ld8s_i32, 1, 1, 1, 0)
50 DEF(ld16u_i32, 1, 1, 1, 0)
51 DEF(ld16s_i32, 1, 1, 1, 0)
52 DEF(ld_i32, 1, 1, 1, 0)
53 DEF(st8_i32, 0, 2, 1, TCG_OPF_SIDE_EFFECTS)
54 DEF(st16_i32, 0, 2, 1, TCG_OPF_SIDE_EFFECTS)
55 DEF(st_i32, 0, 2, 1, TCG_OPF_SIDE_EFFECTS)
57 DEF(add_i32, 1, 2, 0, 0)
58 DEF(sub_i32, 1, 2, 0, 0)
59 DEF(mul_i32, 1, 2, 0, 0)
61 DEF(div_i32, 1, 2, 0, 0)
62 DEF(divu_i32, 1, 2, 0, 0)
63 DEF(rem_i32, 1, 2, 0, 0)
64 DEF(remu_i32, 1, 2, 0, 0)
67 DEF(div2_i32, 2, 3, 0, 0)
68 DEF(divu2_i32, 2, 3, 0, 0)
70 DEF(and_i32, 1, 2, 0, 0)
71 DEF(or_i32, 1, 2, 0, 0)
72 DEF(xor_i32, 1, 2, 0, 0)
74 DEF(shl_i32, 1, 2, 0, 0)
75 DEF(shr_i32, 1, 2, 0, 0)
76 DEF(sar_i32, 1, 2, 0, 0)
78 DEF(rotl_i32, 1, 2, 0, 0)
79 DEF(rotr_i32, 1, 2, 0, 0)
82 DEF(brcond_i32, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
84 DEF(add2_i32, 2, 4, 0, 0)
85 DEF(sub2_i32, 2, 4, 0, 0)
86 DEF(brcond2_i32, 0, 4, 2, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
87 DEF(mulu2_i32, 2, 2, 0, 0)
88 DEF(setcond2_i32, 1, 4, 1, 0)
91 DEF(ext8s_i32, 1, 1, 0, 0)
94 DEF(ext16s_i32, 1, 1, 0, 0)
97 DEF(ext8u_i32, 1, 1, 0, 0)
100 DEF(ext16u_i32, 1, 1, 0, 0)
103 DEF(bswap16_i32, 1, 1, 0, 0)
106 DEF(bswap32_i32, 1, 1, 0, 0)
109 DEF(not_i32, 1, 1, 0, 0)
112 DEF(neg_i32, 1, 1, 0, 0)
115 DEF(andc_i32, 1, 2, 0, 0)
118 DEF(orc_i32, 1, 2, 0, 0)
121 DEF(eqv_i32, 1, 2, 0, 0)
124 DEF(nand_i32, 1, 2, 0, 0)
127 DEF(nor_i32, 1, 2, 0, 0)
131 DEF(mov_i64, 1, 1, 0, 0)
132 DEF(movi_i64, 1, 0, 1, 0)
133 DEF(setcond_i64, 1, 2, 1, 0)
135 DEF(ld8u_i64, 1, 1, 1, 0)
136 DEF(ld8s_i64, 1, 1, 1, 0)
137 DEF(ld16u_i64, 1, 1, 1, 0)
138 DEF(ld16s_i64, 1, 1, 1, 0)
139 DEF(ld32u_i64, 1, 1, 1, 0)
140 DEF(ld32s_i64, 1, 1, 1, 0)
141 DEF(ld_i64, 1, 1, 1, 0)
142 DEF(st8_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS)
143 DEF(st16_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS)
144 DEF(st32_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS)
145 DEF(st_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS)
147 DEF(add_i64, 1, 2, 0, 0)
148 DEF(sub_i64, 1, 2, 0, 0)
149 DEF(mul_i64, 1, 2, 0, 0)
151 DEF(div_i64, 1, 2, 0, 0)
152 DEF(divu_i64, 1, 2, 0, 0)
153 DEF(rem_i64, 1, 2, 0, 0)
154 DEF(remu_i64, 1, 2, 0, 0)
157 DEF(div2_i64, 2, 3, 0, 0)
158 DEF(divu2_i64, 2, 3, 0, 0)
160 DEF(and_i64, 1, 2, 0, 0)
161 DEF(or_i64, 1, 2, 0, 0)
162 DEF(xor_i64, 1, 2, 0, 0)
164 DEF(shl_i64, 1, 2, 0, 0)
165 DEF(shr_i64, 1, 2, 0, 0)
166 DEF(sar_i64, 1, 2, 0, 0)
168 DEF(rotl_i64, 1, 2, 0, 0)
169 DEF(rotr_i64, 1, 2, 0, 0)
172 DEF(brcond_i64, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
174 DEF(ext8s_i64, 1, 1, 0, 0)
177 DEF(ext16s_i64, 1, 1, 0, 0)
180 DEF(ext32s_i64, 1, 1, 0, 0)
183 DEF(ext8u_i64, 1, 1, 0, 0)
186 DEF(ext16u_i64, 1, 1, 0, 0)
189 DEF(ext32u_i64, 1, 1, 0, 0)
192 DEF(bswap16_i64, 1, 1, 0, 0)
195 DEF(bswap32_i64, 1, 1, 0, 0)
198 DEF(bswap64_i64, 1, 1, 0, 0)
201 DEF(not_i64, 1, 1, 0, 0)
204 DEF(neg_i64, 1, 1, 0, 0)
207 DEF(andc_i64, 1, 2, 0, 0)
210 DEF(orc_i64, 1, 2, 0, 0)
213 DEF(eqv_i64, 1, 2, 0, 0)
216 DEF(nand_i64, 1, 2, 0, 0)
219 DEF(nor_i64, 1, 2, 0, 0)
225 DEF(debug_insn_start, 0, 0, 2, 0)
227 DEF(debug_insn_start, 0, 0, 1, 0)
229 DEF(exit_tb, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
230 DEF(goto_tb, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
235 DEF(qemu_ld8u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
237 DEF(qemu_ld8u, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
240 DEF(qemu_ld8s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
242 DEF(qemu_ld8s, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
245 DEF(qemu_ld16u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
247 DEF(qemu_ld16u, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
250 DEF(qemu_ld16s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
252 DEF(qemu_ld16s, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
255 DEF(qemu_ld32, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
257 DEF(qemu_ld32, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
260 DEF(qemu_ld64, 2, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
262 DEF(qemu_ld64, 2, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
266 DEF(qemu_st8, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
268 DEF(qemu_st8, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
271 DEF(qemu_st16, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
273 DEF(qemu_st16, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
276 DEF(qemu_st32, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
278 DEF(qemu_st32, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
281 DEF(qemu_st64, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
283 DEF(qemu_st64, 0, 4, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
288 DEF(qemu_ld8u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
289 DEF(qemu_ld8s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
290 DEF(qemu_ld16u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
291 DEF(qemu_ld16s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
292 DEF(qemu_ld32, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
293 DEF(qemu_ld32u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
294 DEF(qemu_ld32s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
295 DEF(qemu_ld64, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
297 DEF(qemu_st8, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
298 DEF(qemu_st16, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
299 DEF(qemu_st32, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
300 DEF(qemu_st64, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
304 #undef DEF

Indexes created Tue Jul 24 14:28:13 CEST 2018