Cross Reference: /vbox/src/recompiler/target-i386/translate.c

Lines Matching defs:cpu_tmp0
87 static TCGv cpu_tmp0, cpu_tmp4;
483         tcg_gen_addi_tl(cpu_tmp0, cpu_regs[reg], val);
484         tcg_gen_ext16u_tl(cpu_tmp0, cpu_tmp0);
486         tcg_gen_or_tl(cpu_regs[reg], cpu_regs[reg], cpu_tmp0);
489         tcg_gen_addi_tl(cpu_tmp0, cpu_regs[reg], val);
492         tcg_gen_ext32u_tl(cpu_tmp0, cpu_tmp0);
493         tcg_gen_mov_tl(cpu_regs[reg], cpu_tmp0);
507         tcg_gen_add_tl(cpu_tmp0, cpu_regs[reg], cpu_T[0]);
508         tcg_gen_ext16u_tl(cpu_tmp0, cpu_tmp0);
510         tcg_gen_or_tl(cpu_regs[reg], cpu_regs[reg], cpu_tmp0);
513         tcg_gen_add_tl(cpu_tmp0, cpu_regs[reg], cpu_T[0]);
516         tcg_gen_ext32u_tl(cpu_tmp0, cpu_tmp0);
517         tcg_gen_mov_tl(cpu_regs[reg], cpu_tmp0);
534     tcg_gen_mov_tl(cpu_tmp0, cpu_regs[reg]);
536         tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, shift);
537     tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
611     tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, segs[reg].base));
612     tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
632     tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, segs[reg].base));
633     tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
643     tcg_gen_mov_tl(cpu_tmp0, cpu_regs[reg]);
645         tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, shift);
646     tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
753     /* t0 = cpu_tmp0; */
776     tcg_gen_movi_tl(cpu_tmp0, pc);
777     tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, eip));
888     tcg_gen_mov_tl(cpu_tmp0, cpu_regs[R_ECX]);
889     gen_extu(size + 1, cpu_tmp0);
890     tcg_gen_brcondi_tl(TCG_COND_NE, cpu_tmp0, 0, label1);
895     tcg_gen_mov_tl(cpu_tmp0, cpu_regs[R_ECX]);
896     gen_extu(size + 1, cpu_tmp0);
897     tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, label1);
1035         gen_compute_eflags(cpu_tmp0);
1036         tcg_gen_shri_tl(cpu_T[0], cpu_tmp0, 6);
1037         tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
1051         gen_compute_eflags(cpu_tmp0);
1052         tcg_gen_shri_tl(cpu_T[0], cpu_tmp0, 11); /* CC_O */
1053         tcg_gen_shri_tl(cpu_tmp0, cpu_tmp0, 7); /* CC_S */
1054         tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
1059         gen_compute_eflags(cpu_tmp0);
1060         tcg_gen_shri_tl(cpu_T[0], cpu_tmp0, 11); /* CC_O */
1061         tcg_gen_shri_tl(cpu_tmp4, cpu_tmp0, 7); /* CC_S */
1062         tcg_gen_shri_tl(cpu_tmp0, cpu_tmp0, 6); /* CC_Z */
1064         tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
1144                 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0xff);
1145                 t0 = cpu_tmp0;
1148                 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0xffff);
1149                 t0 = cpu_tmp0;
1153                 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0xffffffff);
1154                 t0 = cpu_tmp0;
1167                 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0x80);
1168                 tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE, cpu_tmp0,
1172                 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0x8000);
1173                 tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE, cpu_tmp0,
1178                 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0x80000000);
1179                 tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE, cpu_tmp0,
1199                 t0 = cpu_tmp0;
1204                 t0 = cpu_tmp0;
1210                 t0 = cpu_tmp0;
1231                 t0 = cpu_tmp0;
1236                 t0 = cpu_tmp0;
1242                 t0 = cpu_tmp0;
1771         tcg_gen_andi_tl(cpu_tmp0, t1, (1 << (3 + ot)) - 1);
1773         tcg_gen_mov_tl(cpu_tmp0, t1);
1782         tcg_gen_shr_tl(cpu_tmp4, t0, cpu_tmp0);
1783         tcg_gen_subfi_tl(cpu_tmp0, data_bits, cpu_tmp0);
1784         tcg_gen_shl_tl(t0, t0, cpu_tmp0);
1786         tcg_gen_shl_tl(cpu_tmp4, t0, cpu_tmp0);
1787         tcg_gen_subfi_tl(cpu_tmp0, data_bits, cpu_tmp0);
1788         tcg_gen_shr_tl(t0, t0, cpu_tmp0);
1809     tcg_gen_xor_tl(cpu_tmp0, t2, t0);
1810     tcg_gen_lshift(cpu_tmp0, cpu_tmp0, 11 - (data_bits - 1));
1811     tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, CC_O);
1812     tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0);
1888         tcg_gen_xor_tl(cpu_tmp0, t1, t0);
1889         tcg_gen_lshift(cpu_tmp0, cpu_tmp0, 11 - (data_bits - 1));
1890         tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, CC_O);
1891         tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0);
2001             tcg_gen_shli_tl(cpu_tmp0, t1, 16);
2002             tcg_gen_or_tl(t0, t0, cpu_tmp0);
2009             tcg_gen_shl_tl(cpu_tmp0, t0, cpu_tmp5);
2013             tcg_gen_or_tl(t0, t0, cpu_tmp0);
2022             tcg_gen_subfi_tl(cpu_tmp0, 32, cpu_tmp5);
2023             tcg_gen_shr_tl(cpu_tmp5, t1, cpu_tmp0);
2947     tcg_gen_addi_tl(cpu_tmp0, cpu_A0, 8);
2948     tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_tmp0, mem_index);
2957     tcg_gen_addi_tl(cpu_tmp0, cpu_A0, 8);
2959     tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_tmp0, mem_index);
3915                         tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0,
3917                         tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp0);
3922                         tcg_gen_qemu_ld16u(cpu_tmp0, cpu_A0,
3924                         tcg_gen_st16_tl(cpu_tmp0, cpu_env, op2_offset +
4066                         tcg_gen_qemu_ld8u(cpu_tmp0, cpu_A0,
4068                     tcg_gen_st8_tl(cpu_tmp0, cpu_env, offsetof(CPUX86State,
4077                         tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0,
4079                         tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp0);
4104                             gen_op_mov_v_reg(ot, cpu_tmp0, rm);
4106                             tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0,
4108                         tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp0);
4822                 tcg_gen_ext8s_tl(cpu_tmp0, cpu_T[0]);
4823                 tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
4834                 tcg_gen_ext16s_tl(cpu_tmp0, cpu_T[0]);
4835                 tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
4849                 tcg_gen_ext32s_tl(cpu_tmp0, cpu_T[0]);
4850                 tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
4865                     tcg_gen_sari_tl(cpu_tmp0, cpu_T[0], 31);
4869                     tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
5149                 tcg_gen_ext32s_tl(cpu_tmp0, cpu_T[0]);
5150                 tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
5161                     tcg_gen_sari_tl(cpu_tmp0, cpu_T[0], 31);
5164                     tcg_gen_sub_tl(cpu_cc_src, cpu_T[1], cpu_tmp0);
5173             tcg_gen_ext16s_tl(cpu_tmp0, cpu_T[0]);
5174             tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
6909             tcg_gen_sari_tl(cpu_tmp0, cpu_T[1], 3 + ot);
6910             tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, ot);
6911             tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
6925             tcg_gen_movi_tl(cpu_tmp0, 1);
6926             tcg_gen_shl_tl(cpu_tmp0, cpu_tmp0, cpu_T[1]);
6927             tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
6931             tcg_gen_movi_tl(cpu_tmp0, 1);
6932             tcg_gen_shl_tl(cpu_tmp0, cpu_tmp0, cpu_T[1]);
6933             tcg_gen_not_tl(cpu_tmp0, cpu_tmp0);
6934             tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
6939             tcg_gen_movi_tl(cpu_tmp0, 1);
6940             tcg_gen_shl_tl(cpu_tmp0, cpu_tmp0, cpu_T[1]);
6941             tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
7231                 gen_compute_eflags(cpu_tmp0);
7232                 tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, CC_Z);
7234                     tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, l1);
7236                     tcg_gen_brcondi_tl(TCG_COND_NE, cpu_tmp0, 0, l1);
7751             tcg_gen_andi_tl(cpu_tmp0, t0, 3);
7755             tcg_gen_brcond_tl(TCG_COND_GE, cpu_tmp0, t1, label1);
7795             tcg_gen_andi_tl(cpu_tmp0, cpu_cc_src, CC_Z);
7797             tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, label1);
8229     cpu_tmp0 = tcg_temp_new();