Cross Reference: /vbox/src/recompiler/target-i386/translate.c

Lines Matching defs:cpu_env
80 static TCGv_ptr cpu_env;
476     tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUState, eip));
576     tcg_gen_ld32u_tl(t0, cpu_env, offsetof(CPUState, segs[reg].newselector) + REG_L_OFFSET);
578     tcg_gen_ld32u_tl(t0, cpu_env, offsetof(CPUState, eflags) + REG_L_OFFSET);
603     tcg_gen_ld32u_tl(cpu_A0, cpu_env, offsetof(CPUState, segs[reg].base) + REG_L_OFFSET);
611     tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, segs[reg].base));
624     tcg_gen_ld_tl(cpu_A0, cpu_env, offsetof(CPUState, segs[reg].base));
632     tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, segs[reg].base));
755     tcg_gen_ld32u_tl(t0, cpu_env, offsetof(CPUState, interrupt_request));
777     tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, eip));
848     tcg_gen_ld32s_tl(cpu_T[0], cpu_env, offsetof(CPUState, df));
2555     tcg_gen_ld32u_tl(cpu_T[0], cpu_env,
2562     tcg_gen_st32_tl(cpu_T[0], cpu_env,
2565     tcg_gen_st_tl(cpu_T[0], cpu_env,
2932     tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset);
2938     tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset);
2946     tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(0)));
2949     tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(1)));
2955     tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(0)));
2958     tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(1)));
2964     tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset);
2965     tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset);
2966     tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset + 8);
2967     tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset + 8);
2972     tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset);
2973     tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset);
2978     tcg_gen_ld_i32(cpu_tmp2_i32, cpu_env, s_offset);
2979     tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, d_offset);
2985     tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset);
3371                 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
3380                 tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,fpregs[reg].mmx));
3385                 tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3395                 tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3402                 tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3414                 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env,
3416                 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env,
3439                 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
3441                 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)));
3442                 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)));
3443                 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)));
3455                 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)));
3456                 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)));
3540                 tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3553                 tcg_gen_ld_i64(cpu_T[0], cpu_env,
3559                 tcg_gen_ld32u_tl(cpu_T[0], cpu_env,
3567                 tcg_gen_ld_i64(cpu_T[0], cpu_env,
3573                 tcg_gen_ld32u_tl(cpu_T[0], cpu_env,
3617                 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
3665                 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0)));
3667                 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(1)));
3671                 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,mmx_t0.MMX_L(0)));
3673                 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,mmx_t0.MMX_L(1)));
3686             tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op2_offset);
3687             tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op1_offset);
3692             tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3700             tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3718             tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3719             tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
3735             tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3758             tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3759             tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
3786                     tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0)));
3795             tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op2_offset);
3811                 tcg_gen_st16_tl(cpu_T[0], cpu_env,
3815                 tcg_gen_st16_tl(cpu_T[0], cpu_env,
3828                 tcg_gen_ld16u_tl(cpu_T[0], cpu_env,
3833                 tcg_gen_ld16u_tl(cpu_T[0], cpu_env,
3869                 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, offsetof(CPUX86State,xmm_regs[rm]));
3873                 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, offsetof(CPUX86State,fpregs[rm].mmx));
3918                         tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, op2_offset +
3924                         tcg_gen_st16_tl(cpu_tmp0, cpu_env, op2_offset +
3947             tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3948             tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
4010                     tcg_gen_ld8u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
4019                     tcg_gen_ld16u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
4029                         tcg_gen_ld_i32(cpu_tmp2_i32, cpu_env,
4040                         tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env,
4054                     tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
4068                     tcg_gen_st8_tl(cpu_tmp0, cpu_env, offsetof(CPUX86State,
4073                         tcg_gen_ld_i32(cpu_tmp2_i32, cpu_env,
4081                     tcg_gen_st_i32(cpu_tmp2_i32, cpu_env,
4086                                         cpu_env, offsetof(CPUX86State,
4090                                         cpu_env, offsetof(CPUX86State,
4094                                         cpu_env, offsetof(CPUX86State,
4098                                         cpu_env, offsetof(CPUX86State,
4109                         tcg_gen_st_i32(cpu_tmp2_i32, cpu_env,
4119                         tcg_gen_st_i64(cpu_tmp1_i64, cpu_env,
4160             tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
4161             tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
4189                         tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0)));
4220             tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
4221             tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
4227             tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
4228             tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
4237             tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
4238             tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
4257             tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
4258             tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
4262             tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
4263             tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
6858         tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, offsetof(CPUState, df));
6862         tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, offsetof(CPUState, df));
7378             tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,ldt.selector));
7401             tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,tr.selector));
7448             tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, gdt.limit));
7451             tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, gdt.base));
7494                 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, idt.limit));
7497                 tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, idt.base));
7602                     tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,gdt.base));
7603                     tcg_gen_st32_tl(cpu_T[1], cpu_env, offsetof(CPUX86State,gdt.limit));
7605                     tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,idt.base));
7606                     tcg_gen_st32_tl(cpu_T[1], cpu_env, offsetof(CPUX86State,idt.limit));
7613             tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,cr[0]) + 4);
7615             tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,cr[0]));
7651                             tcg_gen_ld_tl(cpu_T[0], cpu_env,
7653                             tcg_gen_ld_tl(cpu_T[1], cpu_env,
7655                             tcg_gen_st_tl(cpu_T[1], cpu_env,
7657                             tcg_gen_st_tl(cpu_T[0], cpu_env,
7898                 tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,dr[reg]));
7972                 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, mxcsr));
7974                 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, mxcsr));
8075     cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");