Lines Matching defs:seg_reg

329 static void tss_load_seg(int seg_reg, int selector)
353 if (seg_reg == R_CS) {
361 } else if (seg_reg == R_SS) {
379 cpu_x86_load_seg_cache(env, seg_reg, selector,
384 if (seg_reg == R_SS || seg_reg == R_CS)
388 cpu_x86_load_seg_cache(env, seg_reg, selector,
2652 /* only works if protected mode and not VM86. seg_reg must be != R_CS */
2653 void helper_load_seg(int seg_reg, int selector)
2679 if (seg_reg == R_SS
2685 cpu_x86_load_seg_cache(env, seg_reg, selector, 0, 0, 0);
2687 if (seg_reg == R_SS) {
2694 cpu_x86_load_seg_cache_with_clean_flags(env, seg_reg, selector, 0, 0, e2);
2713 if (seg_reg == R_SS) {
2732 if (seg_reg == R_SS)
2744 cpu_x86_load_seg_cache(env, seg_reg, selector,
3162 static inline void validate_seg(int seg_reg, int cpl)
3170 if ((seg_reg == R_FS || seg_reg == R_GS) &&
3171 (env->segs[seg_reg].selector & 0xfffc) == 0)
3174 e2 = env->segs[seg_reg].flags;
3179 cpu_x86_load_seg_cache(env, seg_reg, 0, 0, 0, 0);
5910 * @param seg_reg Segment register.
5913 void sync_seg(CPUX86State *env1, int seg_reg, int selector)
5925 load_seg_vm(seg_reg, selector);
5930 Assert(env1->segs[seg_reg].newselector == 0);
5941 if (seg_reg == R_CS)
5952 helper_load_seg(seg_reg, selector);
5953 /* We used to use tss_load_seg(seg_reg, selector); which, for some reasons ignored
5959 Assert(env1->segs[seg_reg].newselector == 0);
5966 env1->segs[seg_reg].selector = selector; /* hidden values are now incorrect, but will be resynced when this register is accessed. */
5967 env1->segs[seg_reg].newselector = selector;
5968 Log(("sync_seg: out of sync seg_reg=%d selector=%#x\n", seg_reg, selector));
6404 CPUState *env, int seg_reg)
6408 cpu_x86_load_seg_cache(env, seg_reg, sc->selector,