Lines Matching refs:rem
30 #include <VBox/vmm/rem.h>
245 AssertCompile(RT_SIZEOFMEMB(VM, rem.padding) >= RT_SIZEOFMEMB(VM, rem.s));
275 AssertReleaseMsg(sizeof(pVM->rem.padding) >= sizeof(pVM->rem.s), ("%#x >= %#x; sizeof(Env)=%#x\n", sizeof(pVM->rem.padding), sizeof(pVM->rem.s), sizeof(pVM->rem.s.Env)));
276 AssertReleaseMsg(sizeof(pVM->rem.s.Env) <= REM_ENV_SIZE, ("%#x == %#x\n", sizeof(pVM->rem.s.Env), REM_ENV_SIZE));
277 AssertReleaseMsg(!(RT_OFFSETOF(VM, rem) & 31), ("off=%#x\n", RT_OFFSETOF(VM, rem)));
287 pVM->rem.s.offVM = RT_OFFSETOF(VM, rem.s);
288 pVM->rem.s.Env.pVM = pVM;
290 pVM->rem.s.state |= CPU_RAW_MODE_INIT;
298 * deadlocks. (mostly pgm vs rem locking)
300 rc = PDMR3CritSectInit(pVM, &pVM->rem.s.CritSectRegister, RT_SRC_POS, "REM-Register");
304 pVM->rem.s.pCtx = NULL; /* set when executing code. */
308 ASMAtomicIncU32(&pVM->rem.s.cIgnoreAll);
318 if (!cpu_x86_init(&pVM->rem.s.Env, "vbox"))
324 CPUMGetGuestCpuId(pVCpu, 1, 0, &u32Dummy, &u32Dummy, &pVM->rem.s.Env.cpuid_ext_features, &pVM->rem.s.Env.cpuid_features);
325 CPUMGetGuestCpuId(pVCpu, 0x80000001, 0, &u32Dummy, &u32Dummy, &pVM->rem.s.Env.cpuid_ext3_features, &pVM->rem.s.Env.cpuid_ext2_features);
328 cpu_reset(&pVM->rem.s.Env);
332 pVM->rem.s.Env.cbCodeBuffer = 4096;
333 pVM->rem.s.Env.pvCodeBuffer = RTMemExecAlloc(pVM->rem.s.Env.cbCodeBuffer);
334 AssertMsgReturn(pVM->rem.s.Env.pvCodeBuffer, ("Failed to allocate code buffer!\n"), VERR_NO_MEMORY);
337 cpu_single_env = &pVM->rem.s.Env;
340 pVM->rem.s.u32PendingInterrupt = REM_NO_PENDING_IRQ;
345 pVM->rem.s.iMMIOMemType = cpu_register_io_memory(g_apfnMMIORead, g_apfnMMIOWrite, &pVM->rem.s.Env);
346 AssertReleaseMsg(pVM->rem.s.iMMIOMemType >= 0, ("pVM->rem.s.iMMIOMemType=%d\n", pVM->rem.s.iMMIOMemType));
347 pVM->rem.s.iHandlerMemType = cpu_register_io_memory(g_apfnHandlerRead, g_apfnHandlerWrite, pVM);
348 AssertReleaseMsg(pVM->rem.s.iHandlerMemType >= 0, ("pVM->rem.s.iHandlerMemType=%d\n", pVM->rem.s.iHandlerMemType));
349 Log2(("REM: iMMIOMemType=%d iHandlerMemType=%d\n", pVM->rem.s.iMMIOMemType, pVM->rem.s.iHandlerMemType));
352 ASMAtomicDecU32(&pVM->rem.s.cIgnoreAll);
357 rc = SSMR3RegisterInternal(pVM, "rem", 1, REM_SAVED_STATE_VERSION, sizeof(uint32_t) * 10,
432 STAM_REG(pVM, &pVM->rem.s.Env.StatTbFlush, STAMTYPE_PROFILE, "/REM/TbFlush", STAMUNIT_TICKS_PER_CALL, "profiling tb_flush().");
449 pVM->rem.s.idxPendingList = UINT32_MAX;
450 pVM->rem.s.idxFreeList = 0;
452 for (i = 0 ; i < RT_ELEMENTS(pVM->rem.s.aHandlerNotifications); i++)
454 pCur = &pVM->rem.s.aHandlerNotifications[i];
482 Assert(!pVM->rem.s.fGCPhysLastRamFixed);
483 pVM->rem.s.fGCPhysLastRamFixed = true;
506 cb = pVM->rem.s.GCPhysLastRam + 1;
507 AssertLogRelMsgReturn(cb > pVM->rem.s.GCPhysLastRam,
508 ("GCPhysLastRam=%RGp - out of range\n", pVM->rem.s.GCPhysLastRam),
586 Assert(pVM->rem.s.cIgnoreAll == 0);
587 ASMAtomicIncU32(&pVM->rem.s.cIgnoreAll);
588 cpu_reset(&pVM->rem.s.Env);
589 pVM->rem.s.cInvalidatedPages = 0;
590 ASMAtomicDecU32(&pVM->rem.s.cIgnoreAll);
591 Assert(pVM->rem.s.cIgnoreAll == 0);
594 pVM->rem.s.Env.state &= ~CPU_RAW_RING0;
597 pVM->rem.s.fFlushTBs = true;
612 PREM pRem = &pVM->rem.s;
625 SSMR3PutU32(pSSM, pVM->rem.s.u32PendingInterrupt);
671 ASMAtomicIncU32(&pVM->rem.s.cIgnoreAll);
677 pRem = &pVM->rem.s;
720 rc = SSMR3GetUInt(pSSM, &pVM->rem.s.u32PendingInterrupt);
738 CPUMGetGuestCpuId(pVCpu, 1, 0, &u32Dummy, &u32Dummy, &pVM->rem.s.Env.cpuid_ext_features, &pVM->rem.s.Env.cpuid_features);
739 CPUMGetGuestCpuId(pVCpu, 0x80000001, 0, &u32Dummy, &u32Dummy, &u32Dummy, &pVM->rem.s.Env.cpuid_ext2_features);
744 ASMAtomicDecU32(&pVM->rem.s.cIgnoreAll);
786 interrupt_request = pVM->rem.s.Env.interrupt_request;
788 pVM->rem.s.Env.interrupt_request = 0;
789 cpu_single_step(&pVM->rem.s.Env, 1);
794 GCPtrPC = pVM->rem.s.Env.eip + pVM->rem.s.Env.segs[R_CS].base;
795 fBp = !cpu_breakpoint_remove(&pVM->rem.s.Env, GCPtrPC, BP_GDB);
802 rc = cpu_exec(&pVM->rem.s.Env);
817 rc = pVM->rem.s.rc;
818 pVM->rem.s.rc = VERR_INTERNAL_ERROR;
838 int rc2 = cpu_breakpoint_insert(&pVM->rem.s.Env, GCPtrPC, BP_GDB, NULL);
841 cpu_single_step(&pVM->rem.s.Env, 0);
842 pVM->rem.s.Env.interrupt_request = interrupt_request;
859 if (!cpu_breakpoint_insert(&pVM->rem.s.Env, Address, BP_GDB, NULL))
880 if (!cpu_breakpoint_remove(&pVM->rem.s.Env, Address, BP_GDB))
913 pVM->rem.s.Env.state |= CPU_RAW_HM;
916 fFlushTBs = pVM->rem.s.fFlushTBs;
917 pVM->rem.s.fFlushTBs = false;
923 pVM->rem.s.fFlushTBs = fFlushTBs;
926 int interrupt_request = pVM->rem.s.Env.interrupt_request;
929 cpu_single_step(&pVM->rem.s.Env, 0);
931 Assert(!pVM->rem.s.Env.singlestep_enabled);
937 pVM->rem.s.Env.interrupt_request = CPU_INTERRUPT_SINGLE_INSTR;
938 rc = cpu_exec(&pVM->rem.s.Env);
964 if (pVM->rem.s.Env.watchpoint_hit)
973 RTGCPTR GCPtrPC = pVM->rem.s.Env.eip + pVM->rem.s.Env.segs[R_CS].base;
974 QTAILQ_FOREACH(pBP, &pVM->rem.s.Env.breakpoints, entry)
1019 rc = pVM->rem.s.rc;
1020 pVM->rem.s.rc = VERR_INTERNAL_ERROR;
1036 pVM->rem.s.Env.interrupt_request = interrupt_request;
1042 rc, pVM->rem.s.Env.segs[R_CS].selector, (RTGCPTR)pVM->rem.s.Env.eip));
1059 Assert(pVM->rem.s.fInREM);
1061 cpu_single_step(&pVM->rem.s.Env, 1);
1063 Assert(!pVM->rem.s.Env.singlestep_enabled);
1095 if ( pVM->rem.s.Env.exception_index < 0
1096 || pVM->rem.s.Env.exception_index > 256)
1097 pVM->rem.s.Env.exception_index = -1; /** @todo We need to do similar stuff elsewhere, I think. */
1100 pVM->rem.s.Env.interrupt_request = 0;
1102 pVM->rem.s.Env.interrupt_request = CPU_INTERRUPT_SINGLE_INSTR;
1105 || pVM->rem.s.u32PendingInterrupt != REM_NO_PENDING_IRQ)
1106 pVM->rem.s.Env.interrupt_request |= CPU_INTERRUPT_HARD;
1108 pVM->rem.s.Env.interrupt_request,
1109 pVM->rem.s.Env.halted,
1110 pVM->rem.s.Env.exception_index
1113 rc = cpu_exec(&pVM->rem.s.Env);
1116 pVM->rem.s.Env.interrupt_request,
1117 pVM->rem.s.Env.halted,
1118 pVM->rem.s.Env.exception_index
1144 if (pVM->rem.s.Env.watchpoint_hit)
1153 RTGCPTR GCPtrPC = pVM->rem.s.Env.eip + pVM->rem.s.Env.segs[R_CS].base;
1154 QTAILQ_FOREACH(pBP, &pVM->rem.s.Env.breakpoints, entry)
1219 RTLogPrintf("remR3RunLoggingStep: cpu_exec -> EXCP_RC rc=%Rrc\n", pVM->rem.s.rc);
1220 rc = pVM->rem.s.rc;
1221 pVM->rem.s.rc = VERR_INTERNAL_ERROR;
1237 // cpu_single_step(&pVM->rem.s.Env, 0);
1239 pVM->rem.s.Env.interrupt_request &= ~(CPU_INTERRUPT_SINGLE_INSTR | CPU_INTERRUPT_SINGLE_INSTR_IN_FLIGHT);
1262 if (RT_UNLIKELY(pVM->rem.s.Env.state & CPU_EMULATE_SINGLE_STEP))
1265 Assert(pVM->rem.s.fInREM);
1266 Log2(("REMR3Run: (cs:eip=%04x:%RGv)\n", pVM->rem.s.Env.segs[R_CS].selector, (RTGCPTR)pVM->rem.s.Env.eip));
1269 rc = cpu_exec(&pVM->rem.s.Env);
1302 if (pVM->rem.s.Env.watchpoint_hit)
1311 RTGCPTR GCPtrPC = pVM->rem.s.Env.eip + pVM->rem.s.Env.segs[R_CS].base;
1312 QTAILQ_FOREACH(pBP, &pVM->rem.s.Env.breakpoints, entry)
1324 Log2(("REMR3Run: cpu_exec -> EXCP_EXECUTE_RAW pc=%RGv\n", pVM->rem.s.Env.eip));
1340 Log2(("REMR3Run: cpu_exec -> EXCP_RC rc=%Rrc\n", pVM->rem.s.rc));
1341 rc = pVM->rem.s.rc;
1342 pVM->rem.s.rc = VERR_INTERNAL_ERROR;
1355 Log2(("REMR3Run: returns %Rrc (cs:eip=%04x:%RGv)\n", rc, pVM->rem.s.Env.segs[R_CS].selector, (RTGCPTR)pVM->rem.s.Env.eip));
1384 env->pVM->rem.s.cCanExecuteRaw++;
1648 if (env->pVM->rem.s.cCanExecuteRaw == 1)
1740 if (pVM->rem.s.fIgnoreInvlPg || pVM->rem.s.cIgnoreAll)
1743 Assert(pVM->rem.s.fInREM || pVM->rem.s.fInStateSync);
1750 pCtx = (PCPUMCTX)pVM->rem.s.pCtx;
1811 Assert(env->pVM->rem.s.fInREM);
1830 Assert(env->pVM->rem.s.fInREM);
1859 if (pVM->rem.s.fIgnoreCR3Load || pVM->rem.s.cIgnoreAll)
1861 Assert(pVM->rem.s.fInREM);
1873 pCtx = (PCPUMCTX)pVM->rem.s.pCtx;
1907 if (pVM->rem.s.fIgnoreCpuMode || pVM->rem.s.cIgnoreAll)
1909 Assert(pVM->rem.s.fInREM);
1911 pCtx = (PCPUMCTX)pVM->rem.s.pCtx;
2020 if(pVM->rem.s.uPendingException == uTrap && ++pVM->rem.s.cPendingExceptions > 512)
2026 if(pVM->rem.s.uPendingException != uTrap || pVM->rem.s.uPendingExcptEIP != env->eip || pVM->rem.s.uPendingExcptCR2 != env->cr[2])
2029 pVM->rem.s.cPendingExceptions = 1;
2031 pVM->rem.s.uPendingException = uTrap;
2032 pVM->rem.s.uPendingExcptEIP = env->eip;
2033 pVM->rem.s.uPendingExcptCR2 = env->cr[2];
2037 pVM->rem.s.cPendingExceptions = 0;
2038 pVM->rem.s.uPendingException = uTrap;
2039 pVM->rem.s.uPendingExcptEIP = env->eip;
2040 pVM->rem.s.uPendingExcptCR2 = env->cr[2];
2053 pVM->rem.s.cPendingExceptions = 0;
2054 pVM->rem.s.uPendingException = 0;
2055 pVM->rem.s.uPendingExcptEIP = 0;
2056 pVM->rem.s.uPendingExcptCR2 = 0;
2099 STAM_PROFILE_START(&pVM->rem.s.StatsState, a);
2102 pVM->rem.s.Env.pVCpu = pVCpu;
2103 pCtx = pVM->rem.s.pCtx = CPUMQueryGuestCtxPtr(pVCpu);
2105 Assert(!pVM->rem.s.fInREM);
2106 pVM->rem.s.fInStateSync = true;
2111 if (pVM->rem.s.fFlushTBs)
2114 tb_flush(&pVM->rem.s.Env);
2115 pVM->rem.s.fFlushTBs = false;
2124 pVM->rem.s.Env.regs[R_EAX] = pCtx->rax;
2126 pVM->rem.s.Env.regs[R_ECX] = pCtx->rcx;
2128 pVM->rem.s.Env.regs[R_EDX] = pCtx->rdx;
2130 pVM->rem.s.Env.regs[R_EBX] = pCtx->rbx;
2132 pVM->rem.s.Env.regs[R_ESP] = pCtx->rsp;
2134 pVM->rem.s.Env.regs[R_EBP] = pCtx->rbp;
2136 pVM->rem.s.Env.regs[R_ESI] = pCtx->rsi;
2138 pVM->rem.s.Env.regs[R_EDI] = pCtx->rdi;
2139 pVM->rem.s.Env.regs[8] = pCtx->r8;
2140 pVM->rem.s.Env.regs[9] = pCtx->r9;
2141 pVM->rem.s.Env.regs[10] = pCtx->r10;
2142 pVM->rem.s.Env.regs[11] = pCtx->r11;
2143 pVM->rem.s.Env.regs[12] = pCtx->r12;
2144 pVM->rem.s.Env.regs[13] = pCtx->r13;
2145 pVM->rem.s.Env.regs[14] = pCtx->r14;
2146 pVM->rem.s.Env.regs[15] = pCtx->r15;
2148 pVM->rem.s.Env.eip = pCtx->rip;
2150 pVM->rem.s.Env.eflags = pCtx->rflags.u64;
2153 pVM->rem.s.Env.regs[R_EAX] = pCtx->eax;
2155 pVM->rem.s.Env.regs[R_ECX] = pCtx->ecx;
2157 pVM->rem.s.Env.regs[R_EDX] = pCtx->edx;
2159 pVM->rem.s.Env.regs[R_EBX] = pCtx->ebx;
2161 pVM->rem.s.Env.regs[R_ESP] = pCtx->esp;
2163 pVM->rem.s.Env.regs[R_EBP] = pCtx->ebp;
2165 pVM->rem.s.Env.regs[R_ESI] = pCtx->esi;
2167 pVM->rem.s.Env.regs[R_EDI] = pCtx->edi;
2168 pVM->rem.s.Env.eip = pCtx->eip;
2170 pVM->rem.s.Env.eflags = pCtx->eflags.u32;
2173 pVM->rem.s.Env.cr[2] = pCtx->cr2;
2177 pVM->rem.s.Env.dr[i] = pCtx->dr[i];
2184 pVM->rem.s.Env.hflags &= ~HF_HALTED_MASK;
2192 if (pVM->rem.s.cInvalidatedPages)
2198 pVM->rem.s.fIgnoreCR3Load = true;
2199 pVM->rem.s.fIgnoreInvlPg = true;
2200 for (i = 0; i < pVM->rem.s.cInvalidatedPages; i++)
2202 Log2(("REMR3State: invlpg %RGv\n", pVM->rem.s.aGCPtrInvalidatedPages[i]));
2203 tlb_flush_page(&pVM->rem.s.Env, pVM->rem.s.aGCPtrInvalidatedPages[i]);
2205 pVM->rem.s.fIgnoreInvlPg = false;
2206 pVM->rem.s.fIgnoreCR3Load = false;
2208 pVM->rem.s.cInvalidatedPages = 0;
2215 pVM->rem.s.Env.efer = pCtx->msrEFER;
2216 pVM->rem.s.Env.star = pCtx->msrSTAR;
2217 pVM->rem.s.Env.pat = pCtx->msrPAT;
2219 pVM->rem.s.Env.lstar = pCtx->msrLSTAR;
2220 pVM->rem.s.Env.cstar = pCtx->msrCSTAR;
2221 pVM->rem.s.Env.fmask = pCtx->msrSFMASK;
2222 pVM->rem.s.Env.kernelgsbase = pCtx->msrKERNELGSBASE;
2226 pVM->rem.s.Env.hflags |= HF_LMA_MASK;
2228 pVM->rem.s.Env.hflags &= ~(HF_LMA_MASK | HF_CS64_MASK);
2232 pVM->rem.s.Env.hflags &= ~HF_INHIBIT_IRQ_MASK;
2237 pVM->rem.s.Env.hflags |= HF_INHIBIT_IRQ_MASK;
2246 pVM->rem.s.Env.hflags2 &= ~HF2_NMI_MASK;
2248 pVM->rem.s.Env.hflags2 |= HF2_NMI_MASK;
2254 if (fA20State != RT_BOOL(pVM->rem.s.Env.a20_mask & RT_BIT(20)))
2256 ASMAtomicIncU32(&pVM->rem.s.cIgnoreAll);
2257 cpu_x86_set_a20(&pVM->rem.s.Env, fA20State);
2258 ASMAtomicDecU32(&pVM->rem.s.cIgnoreAll);
2279 pVM->rem.s.fIgnoreCR3Load = true;
2280 tlb_flush(&pVM->rem.s.Env, true);
2281 pVM->rem.s.fIgnoreCR3Load = false;
2287 pVM->rem.s.fIgnoreCR3Load = true;
2288 pVM->rem.s.fIgnoreCpuMode = true;
2289 cpu_x86_update_cr4(&pVM->rem.s.Env, pCtx->cr4);
2290 pVM->rem.s.fIgnoreCpuMode = false;
2291 pVM->rem.s.fIgnoreCR3Load = false;
2296 pVM->rem.s.fIgnoreCR3Load = true;
2297 pVM->rem.s.fIgnoreCpuMode = true;
2298 cpu_x86_update_cr0(&pVM->rem.s.Env, pCtx->cr0);
2299 pVM->rem.s.fIgnoreCpuMode = false;
2300 pVM->rem.s.fIgnoreCR3Load = false;
2305 pVM->rem.s.fIgnoreCR3Load = true;
2306 cpu_x86_update_cr3(&pVM->rem.s.Env, pCtx->cr3);
2307 pVM->rem.s.fIgnoreCR3Load = false;
2312 pVM->rem.s.Env.gdt.base = pCtx->gdtr.pGdt;
2313 pVM->rem.s.Env.gdt.limit = pCtx->gdtr.cbGdt;
2318 pVM->rem.s.Env.idt.base = pCtx->idtr.pIdt;
2319 pVM->rem.s.Env.idt.limit = pCtx->idtr.cbIdt;
2324 pVM->rem.s.Env.sysenter_cs = pCtx->SysEnter.cs;
2325 pVM->rem.s.Env.sysenter_eip = pCtx->SysEnter.eip;
2326 pVM->rem.s.Env.sysenter_esp = pCtx->SysEnter.esp;
2333 pVM->rem.s.Env.ldt.selector = pCtx->ldtr.Sel;
2334 pVM->rem.s.Env.ldt.newselector = 0;
2335 pVM->rem.s.Env.ldt.fVBoxFlags = pCtx->ldtr.fFlags;
2336 pVM->rem.s.Env.ldt.base = pCtx->ldtr.u64Base;
2337 pVM->rem.s.Env.ldt.limit = pCtx->ldtr.u32Limit;
2338 pVM->rem.s.Env.ldt.flags = (pCtx->ldtr.Attr.u & SEL_FLAGS_SMASK) << SEL_FLAGS_SHIFT;
2343 sync_ldtr(&pVM->rem.s.Env, pCtx->ldtr.Sel);
2354 CPUMGetGuestCpuId(pVCpu, 1, 0, &u32Dummy, &u32Dummy, &pVM->rem.s.Env.cpuid_ext_features, &pVM->rem.s.Env.cpuid_features);
2355 CPUMGetGuestCpuId(pVCpu, 0x80000001, 0, &u32Dummy, &u32Dummy, &u32Dummy, &pVM->rem.s.Env.cpuid_ext2_features);
2360 save_raw_fp_state(&pVM->rem.s.Env, (uint8_t *)&pCtx->pXStateR3->x87); /* 'save' is an excellent name. */
2366 pVM->rem.s.Env.tr.selector = pCtx->tr.Sel;
2367 pVM->rem.s.Env.tr.newselector = 0;
2368 pVM->rem.s.Env.tr.fVBoxFlags = pCtx->tr.fFlags;
2369 pVM->rem.s.Env.tr.base = pCtx->tr.u64Base;
2370 pVM->rem.s.Env.tr.limit = pCtx->tr.u32Limit;
2371 pVM->rem.s.Env.tr.flags = (pCtx->tr.Attr.u & SEL_FLAGS_SMASK) << SEL_FLAGS_SHIFT;
2373 pVM->rem.s.Env.tr.flags &= ~DESC_TSS_BUSY_MASK;
2385 cpu_x86_set_cpl(&pVM->rem.s.Env, uCpl);
2412 SYNC_IN_SREG(&pVM->rem.s.Env, CS, &pVM->rem.s.Env.segs[R_CS], &pCtx->cs);
2413 SYNC_IN_SREG(&pVM->rem.s.Env, SS, &pVM->rem.s.Env.segs[R_SS], &pCtx->ss);
2414 SYNC_IN_SREG(&pVM->rem.s.Env, DS, &pVM->rem.s.Env.segs[R_DS], &pCtx->ds);
2415 SYNC_IN_SREG(&pVM->rem.s.Env, ES, &pVM->rem.s.Env.segs[R_ES], &pCtx->es);
2416 SYNC_IN_SREG(&pVM->rem.s.Env, FS, &pVM->rem.s.Env.segs[R_FS], &pCtx->fs);
2417 SYNC_IN_SREG(&pVM->rem.s.Env, GS, &pVM->rem.s.Env.segs[R_GS], &pCtx->gs);
2424 pVM->rem.s.Env.exception_index = -1; /** @todo this won't work :/ */
2436 pVM->rem.s.Env.exception_index = u8TrapNo;
2439 pVM->rem.s.Env.exception_is_int = 0;
2441 pVM->rem.s.Env.exception_is_int = enmType == TRPM_HARDWARE_INT ? 0x42 : 0;
2443 pVM->rem.s.Env.exception_next_eip = pVM->rem.s.Env.eip;
2452 pVM->rem.s.Env.exception_is_int = 1;
2453 pVM->rem.s.Env.exception_next_eip = pCtx->rip + 2;
2457 if (read_byte(&pVM->rem.s.Env, pVM->rem.s.Env.segs[R_CS].base + pCtx->rip) == 0xcc)
2458 pVM->rem.s.Env.exception_next_eip = pCtx->rip + 1;
2463 if (read_byte(&pVM->rem.s.Env, pVM->rem.s.Env.segs[R_CS].base + pCtx->rip) == 0xce)
2464 pVM->rem.s.Env.exception_next_eip = pCtx->rip + 1;
2474 pVM->rem.s.Env.cr[2] = TRPMGetFaultAddress(pVCpu);
2477 pVM->rem.s.Env.error_code = TRPMGetErrorCode(pVCpu);
2482 pVM->rem.s.Env.error_code = 0;
2487 pVM->rem.s.Env.error_code = 0;
2494 Log2(("REMR3State: trap=%02x errcd=%RGv cr2=%RGv nexteip=%RGv%s\n", pVM->rem.s.Env.exception_index, (RTGCPTR)pVM->rem.s.Env.error_code,
2495 (RTGCPTR)pVM->rem.s.Env.cr[2], (RTGCPTR)pVM->rem.s.Env.exception_next_eip, pVM->rem.s.Env.exception_is_int ? " software" : ""));
2502 pVM->rem.s.Env.interrupt_request &= ~(CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB | CPU_INTERRUPT_TIMER);
2503 if ( pVM->rem.s.u32PendingInterrupt != REM_NO_PENDING_IRQ
2505 pVM->rem.s.Env.interrupt_request |= CPU_INTERRUPT_HARD;
2511 pVM->rem.s.fInREM = true;
2512 pVM->rem.s.fInStateSync = false;
2513 pVM->rem.s.cCanExecuteRaw = 0;
2514 STAM_PROFILE_STOP(&pVM->rem.s.StatsState, a);
2533 register PCPUMCTX pCtx = pVM->rem.s.pCtx;
2537 STAM_PROFILE_START(&pVM->rem.s.StatsStateBack, a);
2539 Assert(pVM->rem.s.fInREM);
2553 restore_raw_fp_state(&pVM->rem.s.Env, (uint8_t *)&pCtx->pXStateR3->x87);
2558 pCtx->rdi = pVM->rem.s.Env.regs[R_EDI];
2559 pCtx->rsi = pVM->rem.s.Env.regs[R_ESI];
2560 pCtx->rbp = pVM->rem.s.Env.regs[R_EBP];
2561 pCtx->rax = pVM->rem.s.Env.regs[R_EAX];
2562 pCtx->rbx = pVM->rem.s.Env.regs[R_EBX];
2563 pCtx->rdx = pVM->rem.s.Env.regs[R_EDX];
2564 pCtx->rcx = pVM->rem.s.Env.regs[R_ECX];
2565 pCtx->r8 = pVM->rem.s.Env.regs[8];
2566 pCtx->r9 = pVM->rem.s.Env.regs[9];
2567 pCtx->r10 = pVM->rem.s.Env.regs[10];
2568 pCtx->r11 = pVM->rem.s.Env.regs[11];
2569 pCtx->r12 = pVM->rem.s.Env.regs[12];
2570 pCtx->r13 = pVM->rem.s.Env.regs[13];
2571 pCtx->r14 = pVM->rem.s.Env.regs[14];
2572 pCtx->r15 = pVM->rem.s.Env.regs[15];
2574 pCtx->rsp = pVM->rem.s.Env.regs[R_ESP];
2577 pCtx->edi = pVM->rem.s.Env.regs[R_EDI];
2578 pCtx->esi = pVM->rem.s.Env.regs[R_ESI];
2579 pCtx->ebp = pVM->rem.s.Env.regs[R_EBP];
2580 pCtx->eax = pVM->rem.s.Env.regs[R_EAX];
2581 pCtx->ebx = pVM->rem.s.Env.regs[R_EBX];
2582 pCtx->edx = pVM->rem.s.Env.regs[R_EDX];
2583 pCtx->ecx = pVM->rem.s.Env.regs[R_ECX];
2585 pCtx->esp = pVM->rem.s.Env.regs[R_ESP];
2591 pCtx->a_sreg.Sel = pVM->rem.s.Env.segs[R_##a_SREG].selector; \
2592 if (!pVM->rem.s.Env.segs[R_SS].newselector) \
2594 pCtx->a_sreg.ValidSel = pVM->rem.s.Env.segs[R_##a_SREG].selector; \
2596 pCtx->a_sreg.u64Base = pVM->rem.s.Env.segs[R_##a_SREG].base; \
2597 pCtx->a_sreg.u32Limit = pVM->rem.s.Env.segs[R_##a_SREG].limit; \
2599 pCtx->a_sreg.Attr.u = (pVM->rem.s.Env.segs[R_##a_SREG].flags >> SEL_FLAGS_SHIFT) & SEL_FLAGS_SMASK; \
2616 pCtx->rip = pVM->rem.s.Env.eip;
2617 pCtx->rflags.u64 = pVM->rem.s.Env.eflags;
2619 pCtx->eip = pVM->rem.s.Env.eip;
2620 pCtx->eflags.u32 = pVM->rem.s.Env.eflags;
2623 pCtx->cr0 = pVM->rem.s.Env.cr[0];
2624 pCtx->cr2 = pVM->rem.s.Env.cr[2];
2625 pCtx->cr3 = pVM->rem.s.Env.cr[3];
2627 if (((pVM->rem.s.Env.cr[4] ^ pCtx->cr4) & X86_CR4_VME) && !HMIsEnabled(pVM))
2630 pCtx->cr4 = pVM->rem.s.Env.cr[4];
2633 pCtx->dr[i] = pVM->rem.s.Env.dr[i];
2635 pCtx->gdtr.cbGdt = pVM->rem.s.Env.gdt.limit;
2636 if (pCtx->gdtr.pGdt != pVM->rem.s.Env.gdt.base)
2638 pCtx->gdtr.pGdt = pVM->rem.s.Env.gdt.base;
2646 pCtx->idtr.cbIdt = pVM->rem.s.Env.idt.limit;
2647 if (pCtx->idtr.pIdt != pVM->rem.s.Env.idt.base)
2649 pCtx->idtr.pIdt = pVM->rem.s.Env.idt.base;
2657 if ( pCtx->ldtr.Sel != pVM->rem.s.Env.ldt.selector
2658 || pCtx->ldtr.ValidSel != pVM->rem.s.Env.ldt.selector
2659 || pCtx->ldtr.u64Base != pVM->rem.s.Env.ldt.base
2660 || pCtx->ldtr.u32Limit != pVM->rem.s.Env.ldt.limit
2661 || pCtx->ldtr.Attr.u != ((pVM->rem.s.Env.ldt.flags >> SEL_FLAGS_SHIFT) & SEL_FLAGS_SMASK)
2665 pCtx->ldtr.Sel = pVM->rem.s.Env.ldt.selector;
2666 pCtx->ldtr.ValidSel = pVM->rem.s.Env.ldt.selector;
2668 pCtx->ldtr.u64Base = pVM->rem.s.Env.ldt.base;
2669 pCtx->ldtr.u32Limit = pVM->rem.s.Env.ldt.limit;
2670 pCtx->ldtr.Attr.u = (pVM->rem.s.Env.ldt.flags >> SEL_FLAGS_SHIFT) & SEL_FLAGS_SMASK;
2678 if ( pCtx->tr.Sel != pVM->rem.s.Env.tr.selector
2679 || pCtx->tr.ValidSel != pVM->rem.s.Env.tr.selector
2680 || pCtx->tr.u64Base != pVM->rem.s.Env.tr.base
2681 || pCtx->tr.u32Limit != pVM->rem.s.Env.tr.limit
2683 || pCtx->tr.Attr.u != ( (pVM->rem.s.Env.tr.flags >> SEL_FLAGS_SHIFT) & (SEL_FLAGS_SMASK & ~DESC_INTEL_UNUSABLE)
2684 ? (pVM->rem.s.Env.tr.flags | DESC_TSS_BUSY_MASK) >> SEL_FLAGS_SHIFT
2691 pVM->rem.s.Env.tr.selector, (uint64_t)pVM->rem.s.Env.tr.base, pVM->rem.s.Env.tr.limit,
2692 (pVM->rem.s.Env.tr.flags >> SEL_FLAGS_SHIFT) & (SEL_FLAGS_SMASK & ~DESC_INTEL_UNUSABLE)
2693 ? (pVM->rem.s.Env.tr.flags | DESC_TSS_BUSY_MASK) >> SEL_FLAGS_SHIFT : 0));
2694 pCtx->tr.Sel = pVM->rem.s.Env.tr.selector;
2695 pCtx->tr.ValidSel = pVM->rem.s.Env.tr.selector;
2697 pCtx->tr.u64Base = pVM->rem.s.Env.tr.base;
2698 pCtx->tr.u32Limit = pVM->rem.s.Env.tr.limit;
2699 pCtx->tr.Attr.u = (pVM->rem.s.Env.tr.flags >> SEL_FLAGS_SHIFT) & SEL_FLAGS_SMASK;
2710 pCtx->SysEnter.cs = pVM->rem.s.Env.sysenter_cs;
2711 pCtx->SysEnter.eip = pVM->rem.s.Env.sysenter_eip;
2712 pCtx->SysEnter.esp = pVM->rem.s.Env.sysenter_esp;
2715 pCtx->msrEFER = pVM->rem.s.Env.efer;
2716 pCtx->msrSTAR = pVM->rem.s.Env.star;
2717 pCtx->msrPAT = pVM->rem.s.Env.pat;
2719 pCtx->msrLSTAR = pVM->rem.s.Env.lstar;
2720 pCtx->msrCSTAR = pVM->rem.s.Env.cstar;
2721 pCtx->msrSFMASK = pVM->rem.s.Env.fmask;
2722 pCtx->msrKERNELGSBASE = pVM->rem.s.Env.kernelgsbase;
2726 if (pVM->rem.s.Env.hflags & HF_INHIBIT_IRQ_MASK)
2739 if (pVM->rem.s.Env.hflags2 & HF2_NMI_MASK)
2755 if ( pVM->rem.s.Env.exception_index >= 0
2756 && pVM->rem.s.Env.exception_index < 256)
2761 Log(("REMR3StateBack: Pending trap %x %d\n", pVM->rem.s.Env.exception_index, pVM->rem.s.Env.exception_is_int));
2762 TRPMEVENT enmType = pVM->rem.s.Env.exception_is_int ? TRPM_SOFTWARE_INT : TRPM_TRAP;
2763 rc = TRPMAssertTrap(pVCpu, pVM->rem.s.Env.exception_index, enmType);
2767 switch (pVM->rem.s.Env.exception_index)
2774 TRPMSetErrorCode(pVCpu, pVM->rem.s.Env.error_code);
2785 || ( pVM->rem.s.Env.segs[R_SS].newselector
2786 | pVM->rem.s.Env.segs[R_GS].newselector
2787 | pVM->rem.s.Env.segs[R_FS].newselector
2788 | pVM->rem.s.Env.segs[R_ES].newselector
2789 | pVM->rem.s.Env.segs[R_DS].newselector
2790 | pVM->rem.s.Env.segs[R_CS].newselector) == 0
2793 pVM->rem.s.fInREM = false;
2794 pVM->rem.s.pCtx = NULL;
2795 pVM->rem.s.Env.pVCpu = NULL;
2796 STAM_PROFILE_STOP(&pVM->rem.s.StatsStateBack, a);
2808 register PCPUMCTX pCtx = pVM->rem.s.pCtx;
2811 Assert(pVM->rem.s.fInREM);
2829 restore_raw_fp_state(&pVM->rem.s.Env, (uint8_t *)pFpuCtx);
2833 pCtx->rdi = pVM->rem.s.Env.regs[R_EDI];
2834 pCtx->rsi = pVM->rem.s.Env.regs[R_ESI];
2835 pCtx->rbp = pVM->rem.s.Env.regs[R_EBP];
2836 pCtx->rax = pVM->rem.s.Env.regs[R_EAX];
2837 pCtx->rbx = pVM->rem.s.Env.regs[R_EBX];
2838 pCtx->rdx = pVM->rem.s.Env.regs[R_EDX];
2839 pCtx->rcx = pVM->rem.s.Env.regs[R_ECX];
2840 pCtx->r8 = pVM->rem.s.Env.regs[8];
2841 pCtx->r9 = pVM->rem.s.Env.regs[9];
2842 pCtx->r10 = pVM->rem.s.Env.regs[10];
2843 pCtx->r11 = pVM->rem.s.Env.regs[11];
2844 pCtx->r12 = pVM->rem.s.Env.regs[12];
2845 pCtx->r13 = pVM->rem.s.Env.regs[13];
2846 pCtx->r14 = pVM->rem.s.Env.regs[14];
2847 pCtx->r15 = pVM->rem.s.Env.regs[15];
2849 pCtx->rsp = pVM->rem.s.Env.regs[R_ESP];
2851 pCtx->edi = pVM->rem.s.Env.regs[R_EDI];
2852 pCtx->esi = pVM->rem.s.Env.regs[R_ESI];
2853 pCtx->ebp = pVM->rem.s.Env.regs[R_EBP];
2854 pCtx->eax = pVM->rem.s.Env.regs[R_EAX];
2855 pCtx->ebx = pVM->rem.s.Env.regs[R_EBX];
2856 pCtx->edx = pVM->rem.s.Env.regs[R_EDX];
2857 pCtx->ecx = pVM->rem.s.Env.regs[R_ECX];
2859 pCtx->esp = pVM->rem.s.Env.regs[R_ESP];
2870 pCtx->rip = pVM->rem.s.Env.eip;
2871 pCtx->rflags.u64 = pVM->rem.s.Env.eflags;
2873 pCtx->eip = pVM->rem.s.Env.eip;
2874 pCtx->eflags.u32 = pVM->rem.s.Env.eflags;
2877 pCtx->cr0 = pVM->rem.s.Env.cr[0];
2878 pCtx->cr2 = pVM->rem.s.Env.cr[2];
2879 pCtx->cr3 = pVM->rem.s.Env.cr[3];
2881 if (((pVM->rem.s.Env.cr[4] ^ pCtx->cr4) & X86_CR4_VME) && !HMIsEnabled(pVM))
2884 pCtx->cr4 = pVM->rem.s.Env.cr[4];
2887 pCtx->dr[i] = pVM->rem.s.Env.dr[i];
2889 pCtx->gdtr.cbGdt = pVM->rem.s.Env.gdt.limit;
2890 if (pCtx->gdtr.pGdt != (RTGCPTR)pVM->rem.s.Env.gdt.base)
2892 pCtx->gdtr.pGdt = (RTGCPTR)pVM->rem.s.Env.gdt.base;
2900 pCtx->idtr.cbIdt = pVM->rem.s.Env.idt.limit;
2901 if (pCtx->idtr.pIdt != (RTGCPTR)pVM->rem.s.Env.idt.base)
2903 pCtx->idtr.pIdt = (RTGCPTR)pVM->rem.s.Env.idt.base;
2911 if ( pCtx->ldtr.Sel != pVM->rem.s.Env.ldt.selector
2912 || pCtx->ldtr.ValidSel != pVM->rem.s.Env.ldt.selector
2913 || pCtx->ldtr.u64Base != pVM->rem.s.Env.ldt.base
2914 || pCtx->ldtr.u32Limit != pVM->rem.s.Env.ldt.limit
2915 || pCtx->ldtr.Attr.u != ((pVM->rem.s.Env.ldt.flags >> SEL_FLAGS_SHIFT) & SEL_FLAGS_SMASK)
2919 pCtx->ldtr.Sel = pVM->rem.s.Env.ldt.selector;
2920 pCtx->ldtr.ValidSel = pVM->rem.s.Env.ldt.selector;
2922 pCtx->ldtr.u64Base = pVM->rem.s.Env.ldt.base;
2923 pCtx->ldtr.u32Limit = pVM->rem.s.Env.ldt.limit;
2924 pCtx->ldtr.Attr.u = (pVM->rem.s.Env.ldt.flags >> SEL_FLAGS_SHIFT) & SEL_FLAGS_SMASK;
2932 if ( pCtx->tr.Sel != pVM->rem.s.Env.tr.selector
2933 || pCtx->tr.ValidSel != pVM->rem.s.Env.tr.selector
2934 || pCtx->tr.u64Base != pVM->rem.s.Env.tr.base
2935 || pCtx->tr.u32Limit != pVM->rem.s.Env.tr.limit
2937 || pCtx->tr.Attr.u != ( (pVM->rem.s.Env.tr.flags >> SEL_FLAGS_SHIFT) & (SEL_FLAGS_SMASK & ~DESC_INTEL_UNUSABLE)
2938 ? (pVM->rem.s.Env.tr.flags | DESC_TSS_BUSY_MASK) >> SEL_FLAGS_SHIFT
2945 pVM->rem.s.Env.tr.selector, (uint64_t)pVM->rem.s.Env.tr.base, pVM->rem.s.Env.tr.limit,
2946 (pVM->rem.s.Env.tr.flags >> SEL_FLAGS_SHIFT) & (SEL_FLAGS_SMASK & ~DESC_INTEL_UNUSABLE)
2947 ? (pVM->rem.s.Env.tr.flags | DESC_TSS_BUSY_MASK) >> SEL_FLAGS_SHIFT : 0));
2948 pCtx->tr.Sel = pVM->rem.s.Env.tr.selector;
2949 pCtx->tr.ValidSel = pVM->rem.s.Env.tr.selector;
2951 pCtx->tr.u64Base = pVM->rem.s.Env.tr.base;
2952 pCtx->tr.u32Limit = pVM->rem.s.Env.tr.limit;
2953 pCtx->tr.Attr.u = (pVM->rem.s.Env.tr.flags >> SEL_FLAGS_SHIFT) & SEL_FLAGS_SMASK;
2964 pCtx->SysEnter.cs = pVM->rem.s.Env.sysenter_cs;
2965 pCtx->SysEnter.eip = pVM->rem.s.Env.sysenter_eip;
2966 pCtx->SysEnter.esp = pVM->rem.s.Env.sysenter_esp;
2969 pCtx->msrEFER = pVM->rem.s.Env.efer;
2970 pCtx->msrSTAR = pVM->rem.s.Env.star;
2971 pCtx->msrPAT = pVM->rem.s.Env.pat;
2973 pCtx->msrLSTAR = pVM->rem.s.Env.lstar;
2974 pCtx->msrCSTAR = pVM->rem.s.Env.cstar;
2975 pCtx->msrSFMASK = pVM->rem.s.Env.fmask;
2976 pCtx->msrKERNELGSBASE = pVM->rem.s.Env.kernelgsbase;
2994 if (pVM->rem.s.fInREM)
3021 if (pVM->rem.s.Env.pVCpu == pVCpu)
3023 ASMAtomicIncU32(&pVM->rem.s.cIgnoreAll);
3024 cpu_x86_set_a20(&pVM->rem.s.Env, fEnable);
3025 ASMAtomicDecU32(&pVM->rem.s.cIgnoreAll);
3055 idxHead = ASMAtomicXchgU32(&pVM->rem.s.idxPendingList, UINT32_MAX);
3058 Assert(idxHead < RT_ELEMENTS(pVM->rem.s.aHandlerNotifications));
3067 idxNext = pVM->rem.s.aHandlerNotifications[idxHead].idxNext;
3068 Assert(idxNext < RT_ELEMENTS(pVM->rem.s.aHandlerNotifications) || idxNext == UINT32_MAX);
3070 pVM->rem.s.aHandlerNotifications[idxHead].idxNext = idxRevHead;
3072 Assert(++c <= RT_ELEMENTS(pVM->rem.s.aHandlerNotifications));
3084 PREMHANDLERNOTIFICATION pCur = &pVM->rem.s.aHandlerNotifications[idxHead];
3127 Assert(idxHead < RT_ELEMENTS(pVM->rem.s.aHandlerNotifications) || (idxHead == UINT32_MAX && c == 0));
3134 idxNext = ASMAtomicUoReadU32(&pVM->rem.s.idxFreeList);
3137 } while (!ASMAtomicCmpXchgU32(&pVM->rem.s.idxFreeList, idxCur, idxNext));
3145 for (c = 0, idxNext = pVM->rem.s.idxFreeList; idxNext != UINT32_MAX;
3146 idxNext = pVM->rem.s.aHandlerNotifications[idxNext].idxNext)
3148 AssertReleaseMsg(c == RT_ELEMENTS(pVM->rem.s.aHandlerNotifications), ("%#x != %#x, idxFreeList=%#x\n", c, RT_ELEMENTS(pVM->rem.s.aHandlerNotifications), pVM->rem.s.idxFreeList));
3183 pVM->rem.s.Env.cr[0] = pVM->rem.s.pCtx->cr0;
3184 pVM->rem.s.Env.cr[2] = pVM->rem.s.pCtx->cr2;
3185 pVM->rem.s.Env.cr[3] = pVM->rem.s.pCtx->cr3;
3186 pVM->rem.s.Env.cr[4] = pVM->rem.s.pCtx->cr4;
3221 if (GCPhys + (cb - 1) > pVM->rem.s.GCPhysLastRam)
3223 AssertReleaseMsg(!pVM->rem.s.fGCPhysLastRamFixed, ("GCPhys=%RGp cb=%RGp\n", GCPhys, cb));
3224 pVM->rem.s.GCPhysLastRam = GCPhys + (cb - 1);
3231 ASMAtomicIncU32(&pVM->rem.s.cIgnoreAll);
3233 PDMCritSectEnter(&pVM->rem.s.CritSectRegister, VERR_SEM_BUSY);
3235 PDMCritSectLeave(&pVM->rem.s.CritSectRegister);
3237 ASMAtomicDecU32(&pVM->rem.s.cIgnoreAll);
3267 ASMAtomicIncU32(&pVM->rem.s.cIgnoreAll);
3269 PDMCritSectEnter(&pVM->rem.s.CritSectRegister, VERR_SEM_BUSY);
3271 PDMCritSectLeave(&pVM->rem.s.CritSectRegister);
3273 ASMAtomicDecU32(&pVM->rem.s.cIgnoreAll);
3299 ASMAtomicIncU32(&pVM->rem.s.cIgnoreAll);
3301 PDMCritSectEnter(&pVM->rem.s.CritSectRegister, VERR_SEM_BUSY);
3303 PDMCritSectLeave(&pVM->rem.s.CritSectRegister);
3305 ASMAtomicDecU32(&pVM->rem.s.cIgnoreAll);
3331 ASMAtomicIncU32(&pVM->rem.s.cIgnoreAll);
3333 PDMCritSectEnter(&pVM->rem.s.CritSectRegister, VERR_SEM_BUSY);
3335 cpu_register_physical_memory_offset(GCPhys, cb, pVM->rem.s.iMMIOMemType, GCPhys);
3337 cpu_register_physical_memory_offset(GCPhys, cb, pVM->rem.s.iHandlerMemType, GCPhys);
3338 PDMCritSectLeave(&pVM->rem.s.CritSectRegister);
3340 ASMAtomicDecU32(&pVM->rem.s.cIgnoreAll);
3379 ASMAtomicIncU32(&pVM->rem.s.cIgnoreAll);
3381 PDMCritSectEnter(&pVM->rem.s.CritSectRegister, VERR_SEM_BUSY);
3399 PDMCritSectLeave(&pVM->rem.s.CritSectRegister);
3401 ASMAtomicDecU32(&pVM->rem.s.cIgnoreAll);
3441 ASMAtomicIncU32(&pVM->rem.s.cIgnoreAll);
3446 PDMCritSectEnter(&pVM->rem.s.CritSectRegister, VERR_SEM_BUSY);
3462 cpu_register_physical_memory_offset(GCPhysNew, cb, pVM->rem.s.iHandlerMemType, GCPhysNew);
3463 PDMCritSectLeave(&pVM->rem.s.CritSectRegister);
3465 ASMAtomicDecU32(&pVM->rem.s.cIgnoreAll);
3504 return (off & PAGE_OFFSET_MASK) == pVM->rem.s.iHandlerMemType
3505 || (off & PAGE_OFFSET_MASK) == pVM->rem.s.iMMIOMemType
3531 if ((ioTLBEntry & ~TARGET_PAGE_MASK) == pVM->rem.s.iHandlerMemType)
3541 (RTGCPTR)pTLBEntry->addr_code, (RTGCPHYS)pTLBEntry->addend, (RTGCPTR)addr, pVM->rem.s.iHandlerMemType, pVM->rem.s.iMMIOMemType, (RTGCPHYS)ioTLBEntry));
3548 (RTGCPTR)pTLBEntry->addr_code, (RTGCPHYS)pTLBEntry->addend, (RTGCPTR)addr, pVM->rem.s.iHandlerMemType, pVM->rem.s.iMMIOMemType);
3946 pVM->rem.s.Env.state |= CPU_EMULATE_SINGLE_STEP;
3948 pVM->rem.s.Env.state &= ~CPU_EMULATE_SINGLE_STEP;
3950 cpu_single_step(&pVM->rem.s.Env, fEnable);
3992 pVM->rem.s.Env.state & CPU_EMULATE_SINGLE_STEP ? "enabled" : "disabled");
4223 Assert(pVM->rem.s.u32PendingInterrupt == REM_NO_PENDING_IRQ);
4224 pVM->rem.s.u32PendingInterrupt = u8Interrupt;
4237 return pVM->rem.s.u32PendingInterrupt;
4250 LogFlow(("REMR3NotifyInterruptSet: fInRem=%d interrupts %s\n", pVM->rem.s.fInREM,
4251 (pVM->rem.s.Env.eflags & IF_MASK) && !(pVM->rem.s.Env.hflags & HF_INHIBIT_IRQ_MASK) ? "enabled" : "disabled"));
4252 if (pVM->rem.s.fInREM)
4271 if (pVM->rem.s.fInREM)
4290 LogFlow(("REMR3NotifyTimerPending: fInRem=%d\n", pVM->rem.s.fInREM));
4292 if (pVM->rem.s.fInREM)
4294 if (pVM->rem.s.Env.pVCpu == pVCpuDst)
4297 ASMAtomicOrS32((int32_t volatile *)&pVM->rem.s.Env.interrupt_request,
4301 LogIt(LOG_INSTANCE, RTLOGGRPFLAGS_LEVEL_5, LOG_GROUP_TM, ("REMR3NotifyTimerPending: pVCpu:%p != pVCpuDst:%p\n", pVM->rem.s.Env.pVCpu, pVCpuDst));
4318 LogFlow(("REMR3NotifyDmaPending: fInRem=%d\n", pVM->rem.s.fInREM));
4319 if (pVM->rem.s.fInREM)
4337 LogFlow(("REMR3NotifyQueuePending: fInRem=%d\n", pVM->rem.s.fInREM));
4338 if (pVM->rem.s.fInREM)
4356 LogFlow(("REMR3NotifyFF: fInRem=%d\n", pVM->rem.s.fInREM));
4357 if (pVM->rem.s.fInREM)
4443 * Raise an RC, force rem exit.
4451 Assert(pVM->rem.s.fInREM);
4453 pVM->rem.s.rc = rc;
4454 cpu_interrupt(&pVM->rem.s.Env, CPU_INTERRUPT_RC);
4488 if (env->pVM->rem.s.u32PendingInterrupt != REM_NO_PENDING_IRQ)
4491 Assert(env->pVM->rem.s.u32PendingInterrupt <= 255);
4492 u8Interrupt = env->pVM->rem.s.u32PendingInterrupt;
4493 env->pVM->rem.s.u32PendingInterrupt = REM_NO_PENDING_IRQ;
4743 if (pVM->rem.s.fInREM)
4805 if (pVM->rem.s.fInREM)
4836 if (pVM->rem.s.fInREM)