Lines Matching defs:u32

107 static void     remR3MMIOWriteU8(void *pvEnv, target_phys_addr_t GCPhys, uint32_t u32);
108 static void remR3MMIOWriteU16(void *pvEnv, target_phys_addr_t GCPhys, uint32_t u32);
109 static void remR3MMIOWriteU32(void *pvEnv, target_phys_addr_t GCPhys, uint32_t u32);
114 static void remR3HandlerWriteU8(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32);
115 static void remR3HandlerWriteU16(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32);
116 static void remR3HandlerWriteU32(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32);
1437 pCtx->eflags.u32 = env->eflags;
2170 pVM->rem.s.Env.eflags = pCtx->eflags.u32;
2620 pCtx->eflags.u32 = pVM->rem.s.Env.eflags;
2874 pCtx->eflags.u32 = pVM->rem.s.Env.eflags;
3820 uint32_t u32 = 0;
3821 int rc = IOMMMIORead(env->pVM, env->pVCpu, GCPhys, &u32, 1);
3823 Log2(("remR3MMIOReadU8: GCPhys=%RGp -> %02x\n", (RTGCPHYS)GCPhys, u32));
3824 return u32;
3831 uint32_t u32 = 0;
3832 int rc = IOMMMIORead(env->pVM, env->pVCpu, GCPhys, &u32, 2);
3834 Log2(("remR3MMIOReadU16: GCPhys=%RGp -> %04x\n", (RTGCPHYS)GCPhys, u32));
3835 return u32;
3842 uint32_t u32 = 0;
3843 int rc = IOMMMIORead(env->pVM, env->pVCpu, GCPhys, &u32, 4);
3845 Log2(("remR3MMIOReadU32: GCPhys=%RGp -> %08x\n", (RTGCPHYS)GCPhys, u32));
3846 return u32;
3850 static void remR3MMIOWriteU8(void *pvEnv, target_phys_addr_t GCPhys, uint32_t u32)
3854 Log2(("remR3MMIOWriteU8: GCPhys=%RGp u32=%#x\n", (RTGCPHYS)GCPhys, u32));
3855 rc = IOMMMIOWrite(env->pVM, env->pVCpu, GCPhys, u32, 1);
3860 static void remR3MMIOWriteU16(void *pvEnv, target_phys_addr_t GCPhys, uint32_t u32)
3864 Log2(("remR3MMIOWriteU16: GCPhys=%RGp u32=%#x\n", (RTGCPHYS)GCPhys, u32));
3865 rc = IOMMMIOWrite(env->pVM, env->pVCpu, GCPhys, u32, 2);
3870 static void remR3MMIOWriteU32(void *pvEnv, target_phys_addr_t GCPhys, uint32_t u32)
3874 Log2(("remR3MMIOWriteU32: GCPhys=%RGp u32=%#x\n", (RTGCPHYS)GCPhys, u32));
3875 rc = IOMMMIOWrite(env->pVM, env->pVCpu, GCPhys, u32, 4);
3903 uint32_t u32;
3905 PGMPhysRead((PVM)pvVM, GCPhys, &u32, sizeof(u32));
3906 return u32;
3909 static void remR3HandlerWriteU8(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32)
3911 Log2(("remR3HandlerWriteU8: GCPhys=%RGp u32=%#x\n", (RTGCPHYS)GCPhys, u32));
3912 PGMPhysWrite((PVM)pvVM, GCPhys, &u32, sizeof(uint8_t));
3915 static void remR3HandlerWriteU16(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32)
3917 Log2(("remR3HandlerWriteU16: GCPhys=%RGp u32=%#x\n", (RTGCPHYS)GCPhys, u32));
3918 PGMPhysWrite((PVM)pvVM, GCPhys, &u32, sizeof(uint16_t));
3921 static void remR3HandlerWriteU32(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32)
3923 Log2(("remR3HandlerWriteU32: GCPhys=%RGp u32=%#x\n", (RTGCPHYS)GCPhys, u32));
3924 PGMPhysWrite((PVM)pvVM, GCPhys, &u32, sizeof(uint32_t));
4639 uint32_t u32 = 0;
4640 int rc = IOMIOPortRead(env->pVM, env->pVCpu, (RTIOPORT)addr, &u32, 1);
4644 Log2(("cpu_inb: addr=%#06x -> %#x\n", addr, u32));
4645 return (uint8_t)u32;
4649 Log(("cpu_inb: addr=%#06x -> %#x rc=%Rrc\n", addr, u32, rc));
4651 return (uint8_t)u32;
4659 uint32_t u32 = 0;
4660 int rc = IOMIOPortRead(env->pVM, env->pVCpu, (RTIOPORT)addr, &u32, 2);
4663 Log2(("cpu_inw: addr=%#06x -> %#x\n", addr, u32));
4664 return (uint16_t)u32;
4668 Log(("cpu_inw: addr=%#06x -> %#x rc=%Rrc\n", addr, u32, rc));
4670 return (uint16_t)u32;
4678 uint32_t u32 = 0;
4679 int rc = IOMIOPortRead(env->pVM, env->pVCpu, (RTIOPORT)addr, &u32, 4);
4682 Log2(("cpu_inl: addr=%#06x -> %#x\n", addr, u32));
4683 return u32;
4687 Log(("cpu_inl: addr=%#06x -> %#x rc=%Rrc\n", addr, u32, rc));
4689 return u32;