Lines Matching refs:vmm

23 #include <VBox/vmm/vmm.h>
24 #include <VBox/vmm/pgm.h>
25 #include <VBox/vmm/hm.h>
26 #include <VBox/vmm/selm.h>
27 #include <VBox/vmm/mm.h>
31 #include <VBox/vmm/vm.h>
230 pVM->vmm.s.aoffSwitchers[iSwitcher] = cbCoreCode;
243 pVM->vmm.s.cbCoreCode = RT_ALIGN_32(cbCoreCode, PAGE_SIZE);
244 pVM->vmm.s.pvCoreCodeR3 = SUPR3ContAlloc(pVM->vmm.s.cbCoreCode >> PAGE_SHIFT, &pVM->vmm.s.pvCoreCodeR0, &pVM->vmm.s.HCPhysCoreCode);
246 if (pVM->vmm.s.pvCoreCodeR3)
248 rc = PGMR3MapIntermediate(pVM, pVM->vmm.s.pvCoreCodeR0, pVM->vmm.s.HCPhysCoreCode, cbCoreCode);
264 paBadTries[i].pvR3 = pVM->vmm.s.pvCoreCodeR3;
265 paBadTries[i].pvR0 = pVM->vmm.s.pvCoreCodeR0;
266 paBadTries[i].HCPhys = pVM->vmm.s.HCPhysCoreCode;
268 pVM->vmm.s.pvCoreCodeR0 = NIL_RTR0PTR;
269 pVM->vmm.s.HCPhysCoreCode = NIL_RTHCPHYS;
270 pVM->vmm.s.pvCoreCodeR3 = SUPR3ContAlloc(pVM->vmm.s.cbCoreCode >> PAGE_SHIFT, &pVM->vmm.s.pvCoreCodeR0, &pVM->vmm.s.HCPhysCoreCode);
271 if (!pVM->vmm.s.pvCoreCodeR3)
273 rc = PGMR3MapIntermediate(pVM, pVM->vmm.s.pvCoreCodeR0, pVM->vmm.s.HCPhysCoreCode, cbCoreCode);
280 paBadTries[i].pvR3 = pVM->vmm.s.pvCoreCodeR3;
281 paBadTries[i].pvR0 = pVM->vmm.s.pvCoreCodeR0;
282 paBadTries[i].HCPhys = pVM->vmm.s.HCPhysCoreCode;
283 paBadTries[i].cb = pVM->vmm.s.cbCoreCode;
306 uint8_t *pbDst = (uint8_t *)pVM->vmm.s.pvCoreCodeR3 + pVM->vmm.s.aoffSwitchers[iSwitcher];
312 pVM->vmm.s.HCPhysCoreCode + pVM->vmm.s.aoffSwitchers[iSwitcher]);
321 rc = MMR3HyperMapHCPhys(pVM, pVM->vmm.s.pvCoreCodeR3, pVM->vmm.s.pvCoreCodeR0, pVM->vmm.s.HCPhysCoreCode,
325 pVM->vmm.s.pvCoreCodeRC = GCPtr;
328 pVM->vmm.s.pvCoreCodeR3, pVM->vmm.s.pvCoreCodeR0, pVM->vmm.s.pvCoreCodeRC, pVM->vmm.s.HCPhysCoreCode, pVM->vmm.s.cbCoreCode));
336 VMMR3SelectSwitcher(pVM, pVM->vmm.s.enmSwitcher);
341 AssertMsgFailed(("PGMR3Map(,%RRv, %RHp, %#x, 0) failed with rc=%Rrc\n", pVM->vmm.s.pvCoreCodeRC, pVM->vmm.s.HCPhysCoreCode, cbCoreCode, rc));
342 SUPR3ContFree(pVM->vmm.s.pvCoreCodeR3, pVM->vmm.s.cbCoreCode >> PAGE_SHIFT);
349 pVM->vmm.s.pvCoreCodeR3 = NULL;
350 pVM->vmm.s.pvCoreCodeR0 = NIL_RTR0PTR;
351 pVM->vmm.s.pvCoreCodeRC = 0;
374 unsigned off = pVM->vmm.s.aoffSwitchers[iSwitcher];
377 pVM->vmm.s.pvCoreCodeR0 + off,
378 (uint8_t *)pVM->vmm.s.pvCoreCodeR3 + off,
379 pVM->vmm.s.pvCoreCodeRC + off,
380 pVM->vmm.s.HCPhysCoreCode + off);
385 (uint8_t *)pVM->vmm.s.pvCoreCodeR3 + off,
386 pVM->vmm.s.HCPhysCoreCode + off);
394 PVMMSWITCHERDEF pSwitcher = papSwitchers[pVM->vmm.s.enmSwitcher];
397 RTRCPTR RCPtr = pVM->vmm.s.pvCoreCodeRC + pVM->vmm.s.aoffSwitchers[pVM->vmm.s.enmSwitcher];
398 pVM->vmm.s.pfnRCToHost = RCPtr + pSwitcher->offRCToHost;
399 pVM->vmm.s.pfnCallTrampolineRC = RCPtr + pSwitcher->offRCCallTrampoline;
858 *uSrc.pu32 = pVM->vmm.s.GCPtrApicBase;
1127 pVM->vmm.s.enmSwitcher = HC_ARCH_BITS == 64 ? VMMSWITCHER_AMD64_STUB : VMMSWITCHER_X86_STUB;
1136 Log(("VMMR3SelectSwitcher: enmSwitcher %d -> %d %s\n", pVM->vmm.s.enmSwitcher, enmSwitcher, pSwitcher->pszDesc));
1137 pVM->vmm.s.enmSwitcher = enmSwitcher;
1139 RTR0PTR pbCodeR0 = (RTR0PTR)pVM->vmm.s.pvCoreCodeR0 + pVM->vmm.s.aoffSwitchers[enmSwitcher]; /** @todo fix the pvCoreCodeR0 type */
1140 pVM->vmm.s.pfnR0ToRawMode = pbCodeR0 + pSwitcher->offR0ToRawMode;
1142 RTRCPTR RCPtr = pVM->vmm.s.pvCoreCodeRC + pVM->vmm.s.aoffSwitchers[enmSwitcher];
1143 pVM->vmm.s.pfnRCToHost = RCPtr + pSwitcher->offRCToHost;
1144 pVM->vmm.s.pfnCallTrampolineRC = RCPtr + pSwitcher->offRCCallTrampoline;
1182 RTR0PTR pbCodeR0 = (RTR0PTR)pVM->vmm.s.pvCoreCodeR0 + pVM->vmm.s.aoffSwitchers[enmSwitcher];