Cross Reference: /vbox/src/VBox/VMM/VMMR3/VMM.cpp

Lines Matching defs:idCpu
299     for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
301         PVMCPU pVCpu = &pVM->aCpus[idCpu];
492     Assert(pVCpu && pVCpu->idCpu == 0);
516         rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_VMMR0_INIT,
562     Assert(pVCpu && pVCpu->idCpu == 0);
656             for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
658                 rc = PGMMapSetPage(pVM, pVM->aCpus[idCpu].vmm.s.pbEMTStackRC, VMM_STACK_SIZE,
686             for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
688                 uint8_t *pbEMTStackR3 = pVM->aCpus[idCpu].vmm.s.pbEMTStackR3;
743     Assert(pVCpu && pVCpu->idCpu == 0);
755         rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_VMMR0_TERM, 0, NULL);
961                 pR0LoggerR3->idCpu = i;
1000  * @returns The VMCPU pointer. NULL if @a idCpu or @a pUVM is invalid.
1003  * @param   idCpu       The ID of the virtual CPU.
1005 VMMR3DECL(PVMCPU) VMMR3GetCpuByIdU(PUVM pUVM, RTCPUID idCpu)
1008     AssertReturn(idCpu < pUVM->cCpus, NULL);
1010     return &pUVM->pVM->aCpus[idCpu];
1355             rc = SUPR3CallVMMR0Fast(pVM->pVMR0, VMMR0_DO_HM_RUN, pVCpu->idCpu);
1390  * @param   idCpu       Virtual CPU to perform SIPI on
1393 DECLCALLBACK(int) vmmR3SendSipi(PVM pVM, VMCPUID idCpu, uint32_t uVector)
1395     PVMCPU pVCpu = VMMGetCpuById(pVM, idCpu);
1412     Log(("vmmR3SendSipi for VCPU %d with vector %x\n", idCpu, uVector));
1424 DECLCALLBACK(int) vmmR3SendInitIpi(PVM pVM, VMCPUID idCpu)
1426     PVMCPU pVCpu = VMMGetCpuById(pVM, idCpu);
1429     Log(("vmmR3SendInitIpi for VCPU %d\n", idCpu));
1442  * @param   idCpu       Virtual CPU to perform SIPI on
1445 VMMR3_INT_DECL(void) VMMR3SendSipi(PVM pVM, VMCPUID idCpu,  uint32_t uVector)
1447     AssertReturnVoid(idCpu < pVM->cCpus);
1449     int rc = VMR3ReqCallNoWait(pVM, idCpu, (PFNRT)vmmR3SendSipi, 3, pVM, idCpu, uVector);
1457  * @param   idCpu       Virtual CPU to perform int IPI on
1459 VMMR3_INT_DECL(void) VMMR3SendInitIpi(PVM pVM, VMCPUID idCpu)
1461     AssertReturnVoid(idCpu < pVM->cCpus);
1463     int rc = VMR3ReqCallNoWait(pVM, idCpu, (PFNRT)vmmR3SendInitIpi, 2, pVM, idCpu);
1569             rc = RTSemEventWait(pVM->vmm.s.pahEvtRendezvousEnterOrdered[pVCpu->idCpu], RT_INDEFINITE_WAIT);
1616             if (pVCpu->idCpu != iFirst)
1620                 rc = RTSemEventWait(pVM->vmm.s.pahEvtRendezvousEnterOrdered[pVCpu->idCpu], RT_INDEFINITE_WAIT);
1669             Assert(cDone == pVCpu->idCpu + 1U);
1670             rc = RTSemEventSignal(pVM->vmm.s.pahEvtRendezvousEnterOrdered[pVCpu->idCpu + 1U]);
1675             Assert(pVM->cCpus - cDone == pVCpu->idCpu);
1892  * @param   idCpu           The ID of the source CPU context (for the address).
1897 VMMR3_INT_DECL(int) VMMR3ReadR0Stack(PVM pVM, VMCPUID idCpu, RTHCUINTPTR R0Addr, void *pvBuf, size_t cbRead)
1899     PVMCPU pVCpu = VMMGetCpuById(pVM, idCpu);
2043         rc = SUPR3CallVMMR0Ex(pVM->pVMR0, pVCpu->idCpu, uOperation, u64Arg, pReqHdr);