Lines Matching defs:pVM
441 static DECLCALLBACK(int) trpmR3Save(PVM pVM, PSSMHANDLE pSSM);
442 static DECLCALLBACK(int) trpmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
444 static DECLCALLBACK(int) trpmR3GuestIDTWriteHandler(PVM pVM, RTGCPTR GCPtr, void *pvPtr, void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser);
452 * @param pVM Pointer to the VM.
454 VMMR3DECL(int) TRPMR3Init(PVM pVM)
463 AssertRelease(sizeof(pVM->trpm.s) <= sizeof(pVM->trpm.padding));
464 AssertRelease(RT_ELEMENTS(pVM->trpm.s.aGuestTrapHandler) == sizeof(pVM->trpm.s.au32IdtPatched)*8);
469 pVM->trpm.s.offVM = RT_OFFSETOF(VM, trpm);
470 pVM->trpm.s.offTRPMCPU = RT_OFFSETOF(VM, aCpus[0].trpm) - RT_OFFSETOF(VM, trpm);
472 for (VMCPUID i = 0; i < pVM->cCpus; i++)
474 PVMCPU pVCpu = &pVM->aCpus[i];
481 pVM->trpm.s.GuestIdtr.pIdt = RTRCPTR_MAX;
482 pVM->trpm.s.pvMonShwIdtRC = RTRCPTR_MAX;
483 pVM->trpm.s.fSafeToDropGuestIDTMonitoring = false;
488 PCFGMNODE pTRPMNode = CFGMR3GetChild(CFGMR3GetRoot(pVM), "TRPM");
494 pVM->trpm.s.fSafeToDropGuestIDTMonitoring = f;
498 if (pVM->trpm.s.fSafeToDropGuestIDTMonitoring)
505 Assert(sizeof(pVM->trpm.s.aIdt) == sizeof(g_aIdt));
506 memcpy(&pVM->trpm.s.aIdt[0], &g_aIdt[0], sizeof(pVM->trpm.s.aIdt));
511 int rc = SSMR3RegisterInternal(pVM, "trpm", 1, TRPM_SAVED_STATE_VERSION, sizeof(TRPM),
522 if (!HMIsEnabled(pVM))
524 STAM_REG(pVM, &pVM->trpm.s.StatRCWriteGuestIDTFault, STAMTYPE_COUNTER, "/TRPM/RC/IDTWritesFault", STAMUNIT_OCCURENCES, "Guest IDT writes the we returned to R3 to handle.");
525 STAM_REG(pVM, &pVM->trpm.s.StatRCWriteGuestIDTHandled, STAMTYPE_COUNTER, "/TRPM/RC/IDTWritesHandled", STAMUNIT_OCCURENCES, "Guest IDT writes that we handled successfully.");
526 STAM_REG(pVM, &pVM->trpm.s.StatSyncIDT, STAMTYPE_PROFILE, "/PROF/TRPM/SyncIDT", STAMUNIT_TICKS_PER_CALL, "Profiling of TRPMR3SyncIDT().");
529 STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x00], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/00", STAMUNIT_TICKS_PER_CALL, "#DE - Divide error.");
530 STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x01], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/01", STAMUNIT_TICKS_PER_CALL, "#DB - Debug (single step and more).");
531 //STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x02], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/02", STAMUNIT_TICKS_PER_CALL, "NMI");
532 STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x03], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/03", STAMUNIT_TICKS_PER_CALL, "#BP - Breakpoint.");
533 STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x04], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/04", STAMUNIT_TICKS_PER_CALL, "#OF - Overflow.");
534 STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x05], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/05", STAMUNIT_TICKS_PER_CALL, "#BR - Bound range exceeded.");
535 STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x06], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/06", STAMUNIT_TICKS_PER_CALL, "#UD - Undefined opcode.");
536 STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x07], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/07", STAMUNIT_TICKS_PER_CALL, "#NM - Device not available (FPU).");
537 //STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x08], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/08", STAMUNIT_TICKS_PER_CALL, "#DF - Double fault.");
538 STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x09], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/09", STAMUNIT_TICKS_PER_CALL, "#?? - Coprocessor segment overrun (obsolete).");
539 STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x0a], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/0a", STAMUNIT_TICKS_PER_CALL, "#TS - Task switch fault.");
540 STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x0b], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/0b", STAMUNIT_TICKS_PER_CALL, "#NP - Segment not present.");
541 STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x0c], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/0c", STAMUNIT_TICKS_PER_CALL, "#SS - Stack segment fault.");
542 STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x0d], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/0d", STAMUNIT_TICKS_PER_CALL, "#GP - General protection fault.");
543 STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x0e], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/0e", STAMUNIT_TICKS_PER_CALL, "#PF - Page fault.");
544 //STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x0f], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/0f", STAMUNIT_TICKS_PER_CALL, "Reserved.");
545 STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x10], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/10", STAMUNIT_TICKS_PER_CALL, "#MF - Math fault..");
546 STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x11], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/11", STAMUNIT_TICKS_PER_CALL, "#AC - Alignment check.");
547 STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x12], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/12", STAMUNIT_TICKS_PER_CALL, "#MC - Machine check.");
548 STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x13], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/13", STAMUNIT_TICKS_PER_CALL, "#XF - SIMD Floating-Point Exception.");
553 rc = MMHyperAlloc(pVM, sizeof(STAMCOUNTER) * 256, sizeof(STAMCOUNTER), MM_TAG_TRPM, (void **)&pVM->trpm.s.paStatForwardedIRQR3);
555 pVM->trpm.s.paStatForwardedIRQRC = MMHyperR3ToRC(pVM, pVM->trpm.s.paStatForwardedIRQR3);
557 STAMR3RegisterF(pVM, &pVM->trpm.s.paStatForwardedIRQR3[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Forwarded interrupts.",
561 if (!HMIsEnabled(pVM))
563 rc = MMHyperAlloc(pVM, sizeof(STAMCOUNTER) * 256, sizeof(STAMCOUNTER), MM_TAG_TRPM, (void **)&pVM->trpm.s.paStatHostIrqR3);
565 pVM->trpm.s.paStatHostIrqRC = MMHyperR3ToRC(pVM, pVM->trpm.s.paStatHostIrqR3);
567 STAMR3RegisterF(pVM, &pVM->trpm.s.paStatHostIrqR3[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
574 if (!HMIsEnabled(pVM))
576 STAM_REG(pVM, &pVM->trpm.s.StatForwardProfR3, STAMTYPE_PROFILE_ADV, "/TRPM/ForwardRaw/ProfR3", STAMUNIT_TICKS_PER_CALL, "Profiling TRPMForwardTrap.");
577 STAM_REG(pVM, &pVM->trpm.s.StatForwardProfRZ, STAMTYPE_PROFILE_ADV, "/TRPM/ForwardRaw/ProfRZ", STAMUNIT_TICKS_PER_CALL, "Profiling TRPMForwardTrap.");
578 STAM_REG(pVM, &pVM->trpm.s.StatForwardFailNoHandler, STAMTYPE_COUNTER, "/TRPM/ForwardRaw/FailNoHandler", STAMUNIT_OCCURENCES,"Failure to forward interrupt in raw mode.");
579 STAM_REG(pVM, &pVM->trpm.s.StatForwardFailPatchAddr, STAMTYPE_COUNTER, "/TRPM/ForwardRaw/FailPatchAddr", STAMUNIT_OCCURENCES,"Failure to forward interrupt in raw mode.");
580 STAM_REG(pVM, &pVM->trpm.s.StatForwardFailR3, STAMTYPE_COUNTER, "/TRPM/ForwardRaw/FailR3", STAMUNIT_OCCURENCES, "Failure to forward interrupt in raw mode.");
581 STAM_REG(pVM, &pVM->trpm.s.StatForwardFailRZ, STAMTYPE_COUNTER, "/TRPM/ForwardRaw/FailRZ", STAMUNIT_OCCURENCES, "Failure to forward interrupt in raw mode.");
583 STAM_REG(pVM, &pVM->trpm.s.StatTrap0dDisasm, STAMTYPE_PROFILE, "/TRPM/RC/Traps/0d/Disasm", STAMUNIT_TICKS_PER_CALL, "Profiling disassembly part of trpmGCTrap0dHandler.");
584 STAM_REG(pVM, &pVM->trpm.s.StatTrap0dRdTsc, STAMTYPE_COUNTER, "/TRPM/RC/Traps/0d/RdTsc", STAMUNIT_OCCURENCES, "Number of RDTSC #GPs.");
592 if (!HMIsEnabled(pVM))
594 PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies on VCPU */
608 * @param pVM Pointer to the VM.
611 VMMR3DECL(void) TRPMR3Relocate(PVM pVM, RTGCINTPTR offDelta)
614 if (HMIsEnabled(pVM))
618 PVMCPU pVCpu = &pVM->aCpus[0];
630 int rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "TRPMGCHandlerInterupt", &aRCPtrs[TRPM_HANDLER_INT]);
633 rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "TRPMGCHandlerGeneric", &aRCPtrs[TRPM_HANDLER_TRAP]);
636 rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "TRPMGCHandlerTrap08", &aRCPtrs[TRPM_HANDLER_TRAP_08]);
639 rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "TRPMGCHandlerTrap12", &aRCPtrs[TRPM_HANDLER_TRAP_12]);
647 PVBOXIDTE pIdte = &pVM->trpm.s.aIdt[0];
649 for (unsigned i = 0; i < RT_ELEMENTS(pVM->trpm.s.aIdt); i++, pIdte++, pIdteTemplate++)
652 && !ASMBitTest(&pVM->trpm.s.au32IdtPatched[0], i)
673 pIdte->Gen.u16SegSel = SELMGetTrap8Selector(pVM);
676 SELMSetTrap8EIP(pVM, Offset);
689 CPUMSetHyperIDTR(pVCpu, VM_RC_ADDR(pVM, &pVM->trpm.s.aIdt[0]), sizeof(pVM->trpm.s.aIdt)-1);
692 if (pVM->trpm.s.pvMonShwIdtRC != RTRCPTR_MAX)
694 rc = PGMHandlerVirtualDeregister(pVM, pVM->trpm.s.pvMonShwIdtRC);
697 pVM->trpm.s.pvMonShwIdtRC = VM_RC_ADDR(pVM, &pVM->trpm.s.aIdt[0]);
698 rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_HYPERVISOR, pVM->trpm.s.pvMonShwIdtRC, pVM->trpm.s.pvMonShwIdtRC + sizeof(pVM->trpm.s.aIdt) - 1,
704 for (uint32_t iTrap = 0; iTrap < RT_ELEMENTS(pVM->trpm.s.aGuestTrapHandler); iTrap++)
706 if (pVM->trpm.s.aGuestTrapHandler[iTrap] != TRPM_INVALID_HANDLER)
708 Log(("TRPMR3Relocate: iGate=%2X Handler %RRv -> %RRv\n", iTrap, pVM->trpm.s.aGuestTrapHandler[iTrap], pVM->trpm.s.aGuestTrapHandler[iTrap] + offDelta));
709 pVM->trpm.s.aGuestTrapHandler[iTrap] += offDelta;
712 if (ASMBitTest(&pVM->trpm.s.au32IdtPatched[0], iTrap))
714 PVBOXIDTE pIdteCur = &pVM->trpm.s.aIdt[iTrap];
726 pVM->trpm.s.paStatForwardedIRQRC += offDelta;
727 pVM->trpm.s.paStatHostIrqRC += offDelta;
737 * @param pVM Pointer to the VM.
739 VMMR3DECL(int) TRPMR3Term(PVM pVM)
741 NOREF(pVM);
765 * @param pVM Pointer to the VM.
767 VMMR3DECL(void) TRPMR3Reset(PVM pVM)
773 if (pVM->trpm.s.GuestIdtr.pIdt != RTRCPTR_MAX)
775 if (!pVM->trpm.s.fSafeToDropGuestIDTMonitoring)
777 int rc = PGMHandlerVirtualDeregister(pVM, pVM->trpm.s.GuestIdtr.pIdt);
780 pVM->trpm.s.GuestIdtr.pIdt = RTRCPTR_MAX;
782 pVM->trpm.s.GuestIdtr.cbIdt = 0;
788 for (VMCPUID i = 0; i < pVM->cCpus; i++)
789 TRPMR3ResetCpu(&pVM->aCpus[i]);
790 memcpy(&pVM->trpm.s.aIdt[0], &g_aIdt[0], sizeof(pVM->trpm.s.aIdt));
791 memset(pVM->trpm.s.aGuestTrapHandler, 0, sizeof(pVM->trpm.s.aGuestTrapHandler));
792 TRPMR3Relocate(pVM, 0);
798 if (!HMIsEnabled(pVM))
800 PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies on VCPU */
814 * @param pVM Pointer to the VM.
820 VMMR3_INT_DECL(int) TRPMR3GetImportRC(PVM pVM, const char *pszSymbol, PRTRCPTR pRCPtrValue)
823 *pRCPtrValue = VM_RC_ADDR(pVM, &pVM->trpm);
825 *pRCPtrValue = VM_RC_ADDR(pVM, &pVM->aCpus[0].trpm);
828 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(VMMGetCpuById(pVM, 0));
829 *pRCPtrValue = VM_RC_ADDR(pVM, pCtx);
833 PCPUMCTX pCtx = CPUMGetHyperCtxPtr(VMMGetCpuById(pVM, 0));
834 *pRCPtrValue = VM_RC_ADDR(pVM, pCtx);
838 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(VMMGetCpuById(pVM, 0));
839 *pRCPtrValue = VM_RC_ADDR(pVM, CPUMCTX2CORE(pCtx));
843 PCPUMCTX pCtx = CPUMGetHyperCtxPtr(VMMGetCpuById(pVM, 0));
844 *pRCPtrValue = VM_RC_ADDR(pVM, CPUMCTX2CORE(pCtx));
857 * @param pVM Pointer to the VM.
860 static DECLCALLBACK(int) trpmR3Save(PVM pVM, PSSMHANDLE pSSM)
862 PTRPM pTrpm = &pVM->trpm.s;
868 for (VMCPUID i = 0; i < pVM->cCpus; i++)
870 PTRPMCPU pTrpmCpu = &pVM->aCpus[i].trpm.s;
881 SSMR3PutBool(pSSM, HMIsEnabled(pVM));
882 PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies 1 VCPU */
908 * @param pVM Pointer to the VM.
913 static DECLCALLBACK(int) trpmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
931 TRPMR3Reset(pVM);
936 PTRPM pTrpm = &pVM->trpm.s;
940 for (VMCPUID i = 0; i < pVM->cCpus; i++)
942 PTRPMCPU pTrpmCpu = &pVM->aCpus[i].trpm.s;
959 PTRPMCPU pTrpmCpu = &pVM->aCpus[0].trpm.s;
986 PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies 1 VCPU */
1045 * @param pVM Pointer to the VM.
1048 VMMR3DECL(int) TRPMR3SyncIDT(PVM pVM, PVMCPU pVCpu)
1050 STAM_PROFILE_START(&pVM->trpm.s.StatSyncIDT, a);
1051 const bool fRawRing0 = EMIsRawRing0Enabled(pVM);
1054 AssertReturn(!HMIsEnabled(pVM), VERR_TRPM_HM_IPE);
1056 if (fRawRing0 && CSAMIsEnabled(pVM))
1062 trpmClearGuestTrapHandler(pVM, iGate);
1065 CSAMR3CheckGates(pVM, 0, 256);
1076 return DBGFSTOP(pVM);
1083 if ( IDTR.pIdt != pVM->trpm.s.GuestIdtr.pIdt
1084 || IDTR.cbIdt != pVM->trpm.s.GuestIdtr.cbIdt)
1087 if (!pVM->trpm.s.fSafeToDropGuestIDTMonitoring)
1092 if (pVM->trpm.s.GuestIdtr.pIdt != RTRCPTR_MAX)
1094 rc = PGMHandlerVirtualDeregister(pVM, pVM->trpm.s.GuestIdtr.pIdt);
1098 rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_WRITE, IDTR.pIdt, IDTR.pIdt + IDTR.cbIdt /* already inclusive */,
1104 CSAMR3RemovePage(pVM, IDTR.pIdt);
1106 CSAMR3RemovePage(pVM, IDTR.pIdt + IDTR.cbIdt);
1108 rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_WRITE, IDTR.pIdt, IDTR.pIdt + IDTR.cbIdt /* already inclusive */,
1116 pVM->trpm.s.GuestIdtr = IDTR;
1129 return DBGFSTOP(pVM);
1133 pVM->trpm.s.aIdt[3].Gen.u2DPL = RT_MAX(Idte3.Gen.u2Dpl, 1);
1135 pVM->trpm.s.aIdt[3].Gen.u2DPL = Idte3.Gen.u2Dpl;
1141 STAM_PROFILE_STOP(&pVM->trpm.s.StatSyncIDT, a);
1155 * @param pVM Pointer to the VM.
1163 static DECLCALLBACK(int) trpmR3GuestIDTWriteHandler(PVM pVM, RTGCPTR GCPtr, void *pvPtr, void *pvBuf, size_t cbBuf,
1169 Assert(!HMIsEnabled(pVM));
1171 VMCPU_FF_SET(VMMGetCpu(pVM), VMCPU_FF_TRPM_SYNC_IDT);
1181 * @param pVM Pointer to the VM.
1184 int trpmR3ClearPassThroughHandler(PVM pVM, unsigned iTrap)
1187 PVMCPU pVCpu = &pVM->aCpus[0];
1188 Assert(!HMIsEnabled(pVM));
1196 rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "TRPMGCHandlerInterupt", &aGCPtrs[TRPM_HANDLER_INT]);
1200 || iTrap >= RT_ELEMENTS(pVM->trpm.s.aIdt))
1205 memcpy(&pVM->trpm.s.aIdt[iTrap], &g_aIdt[iTrap], sizeof(pVM->trpm.s.aIdt[0]));
1208 ASMBitClear(&pVM->trpm.s.au32IdtPatched[0], iTrap);
1211 PVBOXIDTE pIdte = &pVM->trpm.s.aIdt[iTrap];
1244 * @param pVM Pointer to the VM.
1247 VMMR3DECL(uint32_t) TRPMR3QueryGateByHandler(PVM pVM, RTRCPTR GCPtr)
1249 AssertReturn(!HMIsEnabled(pVM), ~0U);
1251 for (uint32_t iTrap = 0; iTrap < RT_ELEMENTS(pVM->trpm.s.aGuestTrapHandler); iTrap++)
1253 if (pVM->trpm.s.aGuestTrapHandler[iTrap] == GCPtr)
1257 if (ASMBitTest(&pVM->trpm.s.au32IdtPatched[0], iTrap))
1259 PVBOXIDTE pIdte = &pVM->trpm.s.aIdt[iTrap];
1274 * @param pVM Pointer to the VM.
1277 VMMR3DECL(RTRCPTR) TRPMR3GetGuestTrapHandler(PVM pVM, unsigned iTrap)
1279 AssertReturn(iTrap < RT_ELEMENTS(pVM->trpm.s.aIdt), TRPM_INVALID_HANDLER);
1280 AssertReturn(!HMIsEnabled(pVM), TRPM_INVALID_HANDLER);
1282 return pVM->trpm.s.aGuestTrapHandler[iTrap];
1291 * @param pVM Pointer to the VM.
1295 VMMR3DECL(int) TRPMR3SetGuestTrapHandler(PVM pVM, unsigned iTrap, RTRCPTR pHandler)
1298 Assert(PATMIsEnabled(pVM) && pVM->cCpus == 1);
1299 AssertReturn(!HMIsEnabled(pVM), VERR_TRPM_HM_IPE);
1300 PVMCPU pVCpu = &pVM->aCpus[0];
1305 if (iTrap >= RT_ELEMENTS(pVM->trpm.s.aIdt))
1311 AssertReturn(pHandler == TRPM_INVALID_HANDLER || PATMIsPatchGCAddr(pVM, pHandler), VERR_INVALID_PARAMETER);
1322 return trpmClearGuestTrapHandler(pVM, iTrap);
1336 if ( EMIsRawRing0Enabled(pVM)
1337 && !EMIsRawRing1Enabled(pVM)) /* can't deal with the ambiguity of ring 1 & 2 in the patch code. */
1375 PVBOXIDTE pIdte = &pVM->trpm.s.aIdt[iTrap];
1384 ASMBitSet(&pVM->trpm.s.au32IdtPatched[0], iTrap);
1387 pVM->trpm.s.aGuestTrapHandler[iTrap] = pHandler;
1405 pVM->trpm.s.aGuestTrapHandler[iTrap] = pHandler;
1417 * @param pVM Pointer to the VM.
1420 VMMR3DECL(bool) TRPMR3IsGateHandler(PVM pVM, RTRCPTR GCPtr)
1423 Assert(PATMIsEnabled(pVM) && pVM->cCpus == 1);
1424 PVMCPU pVCpu = &pVM->aCpus[0];
1461 PGMPhysReleasePageMappingLock(pVM, &Lock);
1477 PGMPhysReleasePageMappingLock(pVM, &Lock);
1496 * @param pVM Pointer to the VM.
1500 VMMR3DECL(int) TRPMR3InjectEvent(PVM pVM, PVMCPU pVCpu, TRPMEVENT enmEvent)
1504 Assert(!PATMIsPatchGCAddr(pVM, pCtx->eip));
1511 if ( !EMIsSupervisorCodeRecompiled(pVM)
1513 && REMR3QueryPendingInterrupt(pVM, pVCpu) == REM_NO_PENDING_IRQ
1520 DBGFR3_INFO_LOG(pVM, "cpumguest", "TRPMInject");
1530 if (HMIsEnabled(pVM))
1535 STAM_COUNTER_INC(&pVM->trpm.s.paStatForwardedIRQR3[u8Interrupt]);
1539 if (pVM->trpm.s.aGuestTrapHandler[u8Interrupt] == TRPM_INVALID_HANDLER)
1541 CSAMR3CheckGates(pVM, u8Interrupt, 1);
1542 Log(("TRPMR3InjectEvent: recheck gate %x -> valid=%d\n", u8Interrupt, TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) != TRPM_INVALID_HANDLER));
1545 if (pVM->trpm.s.aGuestTrapHandler[u8Interrupt] != TRPM_INVALID_HANDLER)
1548 rc = EMR3CheckRawForcedActions(pVM, pVCpu);
1557 STAM_COUNTER_INC(&pVM->trpm.s.paStatForwardedIRQR3[u8Interrupt]);
1563 STAM_COUNTER_INC(&pVM->trpm.s.StatForwardFailNoHandler);
1565 REMR3NotifyPendingInterrupt(pVM, pVCpu, u8Interrupt);
1581 STAM_COUNTER_INC(&pVM->trpm.s.paStatForwardedIRQR3[u8Interrupt]);