Lines Matching defs:enmState
125 Assert(pVCpu->em.s.enmState == EMSTATE_DEBUG_HYPER);
157 Assert( pVCpu->em.s.enmState == EMSTATE_DEBUG_HYPER
158 || pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_RAW
159 || pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_REM);
162 bool fGuest = pVCpu->em.s.enmState != EMSTATE_DEBUG_HYPER;
196 if (pVCpu->em.s.enmState == EMSTATE_DEBUG_HYPER)
234 EMSTATE enmOldState = pVCpu->em.s.enmState;
235 pVCpu->em.s.enmState = EMSTATE_DEBUG_GUEST_RAW;
249 pVCpu->em.s.enmState = enmOldState;
1103 PATMTRANSSTATE enmState;
1104 RTGCPTR pOrgInstrGC = PATMR3PatchToGCPtr(pVM, pCtx->eip, &enmState);
1106 if (enmState == PATMTRANS_OVERWRITTEN)
1113 enmState = PATMTRANS_SAFE;
1117 AssertReleaseMsg(pOrgInstrGC && enmState != PATMTRANS_OVERWRITTEN, ("Unable to translate instruction address at %08RX32\n", pCtx->eip));
1118 if (enmState != PATMTRANS_OVERWRITTEN)
1148 PATMTRANSSTATE enmState;
1149 RTGCPTR pOrgInstrGC = PATMR3PatchToGCPtr(pVM, pCtx->rip, &enmState);
1151 Log(("Force recompiler switch due to cr0 (%RGp) update rip=%RGv -> %RGv (enmState=%d)\n", pCtx->cr0, pCtx->rip, pOrgInstrGC, enmState));
1152 if (enmState == PATMTRANS_OVERWRITTEN)
1158 enmState = PATMTRANS_SAFE;
1161 AssertReleaseMsg(pOrgInstrGC && enmState != PATMTRANS_OVERWRITTEN, ("Unable to translate instruction address at %RGv\n", (RTGCPTR)pCtx->rip));
1162 if (enmState != PATMTRANS_OVERWRITTEN)
1307 Assert(pVCpu->em.s.enmState != EMSTATE_WAIT_SIPI);